soc/intel/alderlake: Hook up UPD DisableSagvReorder

Hook the newly exposed DisableSagvReorder UPD up so that
boards can configure is via devicetree.

BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>

src/soc/intel/alderlake/chip.h

@@ -737,6 +737,13 @@ struct soc_intel_alderlake_config {
 	 * Set this to 1 in order to reduce BasicMemoryTest size
 	 */
 	bool lower_basic_mem_test_size;
+
+	/*
+	 * Enable or Disable SaGV reordering operation.
+	 * Default is set to 0, SaGV reordering enabled.
+	 * Set this to 1 in order to disable SaGV reordering.
+	 */
+	bool disable_sagv_reorder;
 };
 
 typedef struct soc_intel_alderlake_config config_t;

src/soc/intel/alderlake/romstage/fsp_params.c

@@ -160,6 +160,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 	}
 #if CONFIG(SOC_INTEL_RAPTORLAKE)
 	m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size;
+	m_cfg->DisableSagvReorder = config->disable_sagv_reorder;
 #endif
 }