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mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF 

Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports

BUG=none
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
David Wu 2020-10-21 10:42:25 +08:00 committed by Patrick Georgi
parent e738a7e337
commit 7d1a137b84
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -103,10 +103,10 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[1]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
register "PcieClkSrcUsage[2]" = "0xFF" register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[4]" = "0xFF" register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[5]" = "0xFF" register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[6]" = "0xFF" register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA # Enable SATA
register "SataEnable" = "1" register "SataEnable" = "1"