soc/intel/tigerlake: Enable GPIO IOSTANDBY configuration

Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.

BUG=b:171993054

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Duncan Laurie 2020-11-05 10:09:58 -08:00 committed by Duncan Laurie
parent 17e905ac48
commit 7d97136749
1 changed files with 1 additions and 0 deletions

View File

@ -48,6 +48,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_DTT select SOC_INTEL_COMMON_BLOCK_DTT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3