mb/intel/tglrvp: Add TGL UP4 RVP
Add initial TGL UP4 RVP build enviorment BUG=none BRANCH=none TEST= Build TGL UP4 successfully Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iab7ada0746394539586e7cc159112dc8208fdd7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39363 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim
Patrick Georgi
parent
7b6a82dc1a
commit
7e303581bc
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@ -1,4 +1,4 @@
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if BOARD_INTEL_TGLRVP_UP3
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if BOARD_INTEL_TGLRVP_UP3 || BOARD_INTEL_TGLRVP_UP4
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -28,11 +28,13 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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string
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default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3
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default "tglrvp_up4" if BOARD_INTEL_TGLRVP_UP4
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config GBB_HWID
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string
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depends on CHROMEOS
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default "TGLRVP" if BOARD_INTEL_TGLRVP_UP3
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default "TGLRVPUP3" if BOARD_INTEL_TGLRVP_UP3
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default "TGLRVPUP4" if BOARD_INTEL_TGLRVP_UP4
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config MAINBOARD_PART_NUMBER
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string
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@ -1,2 +1,5 @@
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config BOARD_INTEL_TGLRVP_UP3
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bool "Tigerlake UP3 DDR4/LPDDR4 RVP"
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bool "Tigerlake UP3 RVP"
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config BOARD_INTEL_TGLRVP_UP4
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bool "Tigerlake UP4 RVP"
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@ -0,0 +1,20 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019-2020 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -0,0 +1,203 @@
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chip soc/intel/tigerlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# FSP configuration
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register "SaGv" = "SaGv_Disabled"
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register "SmbusEnable" = "1"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1
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register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
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register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
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register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used
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register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used
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register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used
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register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PrmrrSize" = "0x10000000"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[10]" = "1"
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register "PcieClkSrcClkReq[1]" = "1"
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register "PcieClkSrcClkReq[2]" = "2"
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register "PcieClkSrcClkReq[3]" = "3"
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register "PcieClkSrcUsage[1]" = "0x2"
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register "PcieClkSrcUsage[2]" = "0x3"
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register "PcieClkSrcUsage[3]" = "0x8"
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# enabling EDP in PortA
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register "DdiPortAConfig" = "1"
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register "DdiPort1Hpd" = "1"
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register "DdiPort1Ddc" = "1"
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoGSpiCsState" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci,
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}"
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#HD Audio
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register "PchHdaDspEnable" = "1"
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register "PchHdaAudioLinkHdaEnable" = "0"
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register "PchHdaAudioLinkDmicEnable[0]" = "1"
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register "PchHdaAudioLinkDmicEnable[1]" = "1"
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register "PchHdaAudioLinkSspEnable[0]" = "1"
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register "PchHdaAudioLinkSspEnable[1]" = "1"
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# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
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register "PchHdaIDispLinkTmode" = "2"
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# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
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register "PchHdaIDispLinkFrequency" = "4"
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# Not disconnected/enumerable
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register "PchHdaIDispCodecDisconnect" = "0"
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device domain 0 on
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#From EDS(575683)
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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device pci 02.0 on end # Graphics
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device pci 04.0 on end # DPTF 0x9A03
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device pci 05.0 on end # IPU 0x9A19
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device pci 06.0 on end # PEG60 0x9A09
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device pci 07.0 off end # TBT_PCIe0 0x9A23
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device pci 07.1 off end # TBT_PCIe1 0x9A25
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device pci 07.2 off end # TBT_PCIe2 0x9A27
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device pci 07.3 off end # TBT_PCIe3 0x9A29
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device pci 08.0 off end # GNA 0x9A11
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device pci 09.0 off end # NPK 0x9A33
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device pci 0a.0 off end # Crash-log SRAM 0x9A0D
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device pci 0d.0 on end # USB xHCI 0x9A13
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device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
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device pci 0d.2 off end # TBT DMA0 0x9A1B
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device pci 0d.3 off end # TBT DMA1 0x9A1D
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device pci 0e.0 on end # VMD 0x9A0B
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# From PCH EDS(576591)
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device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7
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device pci 10.6 off end # THC0 0xA0D0
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device pci 10.7 off end # THC1 0xA0D1
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device pci 12.0 off end # SensorHUB 0xA0FC
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device pci 12.6 off end # GSPI2 0x34FB
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device pci 13.0 off end # GSPI3 0xA0FD
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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device pci 14.1 on end # USB3.1 xDCI 0xA0EE
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device pci 14.2 on end # Shared RAM 0xA0EF
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device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3
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device pci 15.0 on # I2C0 0xA0E8
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "4"
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register "imon_slot_no" = "5"
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register "uid" = "0"
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register "desc" = ""RIGHT SPEAKER AMP""
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register "name" = ""MAXR""
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device i2c 31 on end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "6"
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register "imon_slot_no" = "7"
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register "uid" = "1"
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register "desc" = ""LEFT SPEAKER AMP""
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register "name" = ""MAXL""
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device i2c 32 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Realtek RT5682""
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register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_C12_IRQ)"
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register "probed" = "1"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on end
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end
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end # I2C0
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device pci 15.1 on end # I2C1 0xA0E9
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device pci 15.2 on end # I2C2 0xA0EA
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device pci 15.3 on end # I2C3 0xA0EB
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device pci 16.0 on end # HECI1 0xA0E0
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device pci 16.1 off end # HECI2 0xA0E1
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device pci 16.2 off end # CSME 0xA0E2
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device pci 16.3 off end # CSME 0xA0E3
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device pci 16.4 off end # HECI3 0xA0E4
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device pci 16.5 off end # HECI4 0xA0E5
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device pci 17.0 on end # SATA 0xA0D3
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device pci 19.0 off end # I2C4 0xA0C5
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device pci 19.1 on end # I2C5 0xA0C6
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device pci 19.2 on end # UART2 0xA0C7
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device pci 1c.0 off end # RP1 0xA0B8
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device pci 1c.1 off end # RP2 0xA0B9
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device pci 1c.2 on end # RP3 0xA0BA
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device pci 1c.3 on end # RP4 0xA0BB
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device pci 1c.4 off end # RP5 0xA0BC
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device pci 1c.5 off end # RP6 0xA0BD
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device pci 1c.6 off end # RP7 0xA0BE
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device pci 1c.7 off end # RP8 0xA0BF
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device pci 1d.0 on end # RP9 0xA0B0
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device pci 1d.1 off end # RP10 0xA0B1
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device pci 1d.2 on end # RP11 0xA0B2
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device pci 1d.3 off end # RP12 0xA0B3
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device pci 1e.0 off end # UART0 0xA0A8
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device pci 1e.1 off end # UART1 0xA0A9
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device pci 1e.2 off end # GSPI0 0xA0AA
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device pci 1e.3 off end # GSPI1 0xA0AB
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device pci 1f.0 on end # eSPI 0xA080 - A09F
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device pci 1f.1 on end # P2SB 0xA0A0
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device pci 1f.2 on end # PMC 0xA0A1
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device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
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device pci 1f.4 on end # SMBus 0xA0A3
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device pci 1f.5 on end # SPI 0xA0A4
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device pci 1f.6 off end # GbE 0x15E1/0x15E2
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device pci 1f.7 off end # TH 0xA0A6
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end
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end
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@ -0,0 +1,108 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/* PCH M.2 SSD */
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PAD_CFG_GPO(GPP_B16, 1, PLTRST),
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PAD_CFG_GPO(GPP_H0, 1, PLTRST),
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/* Camera */
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PAD_CFG_GPO(GPP_B23, 0, PLTRST),
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PAD_CFG_GPO(GPP_C15, 0, PLTRST),
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PAD_CFG_GPO(GPP_E22, 0, PLTRST),
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PAD_CFG_GPO(GPP_H12, 0, PLTRST),
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/* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
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PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1),
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/* ISH UART0 RX/TX */
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PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
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/* ISH I2C0 */
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PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1),
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/* ISH GPI 0-6 */
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PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1),
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/*Audio */
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
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PAD_CFG_GPO(GPP_C5, 1, PLTRST),
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PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/*Audio */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */
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PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_HP_RX */
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PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* I2S1_SPKR_SCLK */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S1_SPKR_TX */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S1_SPKR_RX */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S1_SPKR_SFRM */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SNDW0_HP_CLK */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW0_HP_DATA */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), /* SNDW1_SPKR_CLK */
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PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), /* SNDW1_SPKR_DATA */
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PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC1_CLK */
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PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* DMIC1_DATA */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC0_CLK */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC0_DATA */
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};
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const struct pad_config *variant_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
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};
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const struct cros_gpio *variant_cros_gpios(size_t *num)
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{
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*num = ARRAY_SIZE(cros_gpios);
|
||||
return cros_gpios;
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2020 Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <intelblocks/mp_init.h>
|
||||
|
||||
size_t __weak variant_memory_sku(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mb_lpddr4x_cfg mem_config = {
|
||||
/* DQ byte map */
|
||||
.dq_map = {
|
||||
{ 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */
|
||||
15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */
|
||||
{ 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */
|
||||
3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */
|
||||
{ 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */
|
||||
11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */
|
||||
{ 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */
|
||||
4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */
|
||||
{ 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */
|
||||
4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */
|
||||
{ 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */
|
||||
9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */
|
||||
{ 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */
|
||||
10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */
|
||||
{ 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */
|
||||
3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.dqs_map = {
|
||||
/* Ch 0 1 2 3 */
|
||||
{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 },
|
||||
{ 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }
|
||||
},
|
||||
|
||||
.ect = 1, /* Early Command Training */
|
||||
};
|
||||
|
||||
const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
|
||||
{
|
||||
return &mem_config;
|
||||
}
|
||||
Loading…
Reference in New Issue