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Stoney Ridge Platforms: cast AGESA tables to void * 

In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2017-10-16 14:55:53 -06:00
parent c450fbe909
commit 7eb363c505
5 changed files with 9 additions and 9 deletions
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2
src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
View File

@ -47,5 +47,5 @@ static const GPIO_CONTROL oem_gardenia_gpio[] = {
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
{
FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;
}

6
src/mainboard/amd/gardenia/bootblock/OemCustomize.c
View File

@ -102,8 +102,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList
.PciePortList = (void *)PortList,
.DdiLinkList = (void *)DdiList
};
static const UINT32 AzaliaCodecAlc286Table[] = {
@ -150,7 +150,7 @@ static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
/*---------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->PlatformConfig.AzaliaCodecVerbTable =
(uint64_t)(uintptr_t)CodecTableList;
}

2
src/mainboard/google/kahlee/BiosCallOuts.c
View File

@ -23,7 +23,7 @@ extern const GPIO_CONTROL oem_kahlee_gpio[];
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
{
FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio;
/* SDHCI/MMC configuration */
FchParams_env->Sd.SdSlotType = 1; // EMMC

2
src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
View File

@ -23,5 +23,5 @@ extern const GPIO_CONTROL oem_kahlee_gpio[];
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
{
FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio;
}

6
src/mainboard/google/kahlee/bootblock/OemCustomize.c
View File

@ -101,8 +101,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
.Flags = DESCRIPTOR_TERMINATE_LIST,
.SocketId = 0,
.PciePortList = PortList,
.DdiLinkList = DdiList
.PciePortList = (void *)PortList,
.DdiLinkList = (void *)DdiList
};
/*---------------------------------------------------------------------------*/
@ -123,7 +123,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
/*---------------------------------------------------------------------------*/
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
{
InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
}