Stoney Ridge Platforms: cast AGESA tables to void *
In the original AGESA headers, these tables are not defined as const. Cast them to void * so that they'll work with either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22059 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -47,5 +47,5 @@ static const GPIO_CONTROL oem_gardenia_gpio[] = {
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void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
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void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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{
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FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
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FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;
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}
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}
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@ -102,8 +102,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.SocketId = 0,
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.PciePortList = PortList,
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.PciePortList = (void *)PortList,
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.DdiLinkList = DdiList
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.DdiLinkList = (void *)DdiList
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};
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};
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static const UINT32 AzaliaCodecAlc286Table[] = {
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static const UINT32 AzaliaCodecAlc286Table[] = {
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@ -150,7 +150,7 @@ static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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{
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
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InitEarly->PlatformConfig.AzaliaCodecVerbTable =
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InitEarly->PlatformConfig.AzaliaCodecVerbTable =
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(uint64_t)(uintptr_t)CodecTableList;
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(uint64_t)(uintptr_t)CodecTableList;
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}
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}
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@ -23,7 +23,7 @@ extern const GPIO_CONTROL oem_kahlee_gpio[];
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void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
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void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
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{
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{
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FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
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FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio;
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/* SDHCI/MMC configuration */
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/* SDHCI/MMC configuration */
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FchParams_env->Sd.SdSlotType = 1; // EMMC
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FchParams_env->Sd.SdSlotType = 1; // EMMC
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@ -23,5 +23,5 @@ extern const GPIO_CONTROL oem_kahlee_gpio[];
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void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
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void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
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{
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{
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FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
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FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio;
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}
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}
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@ -101,8 +101,8 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.Flags = DESCRIPTOR_TERMINATE_LIST,
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.SocketId = 0,
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.SocketId = 0,
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.PciePortList = PortList,
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.PciePortList = (void *)PortList,
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.DdiLinkList = DdiList
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.DdiLinkList = (void *)DdiList
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};
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};
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@ -123,7 +123,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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{
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
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InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
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InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
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InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
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InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
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}
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}
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