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AGESA f15tn: Factor out default MTRR settings 

All AGESA f15tn boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.

TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.

Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
This commit is contained in:
Angel Pons 2020-05-21 15:24:42 +02:00 committed by Nico Huber
parent 7e577ad22f
commit 7ee8e7f129
7 changed files with 17 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/amd/parmer/buildOpts.c
View File

@ -194,24 +194,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* Include the files that instantiate the configuration definitions. */ /* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h" #include "cpuRegisters.h"
#include "cpuFamRegisters.h" #include "cpuFamRegisters.h"

18
src/mainboard/amd/thatcher/buildOpts.c
View File

@ -194,24 +194,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* Include the files that instantiate the configuration definitions. */ /* Include the files that instantiate the configuration definitions. */
#include "cpuRegisters.h" #include "cpuRegisters.h"
#include "cpuFamRegisters.h" #include "cpuFamRegisters.h"

18
src/mainboard/asus/f2a85-m/buildOpts.c
View File

@ -207,24 +207,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* MEMORY_BUS_SPEED */ /* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533 #define DDR533_FREQUENCY 266 ///< DDR 533

18
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
View File

@ -208,24 +208,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* MEMORY_BUS_SPEED */ /* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533 #define DDR533_FREQUENCY 266 ///< DDR 533

18
src/mainboard/lenovo/g505s/buildOpts.c
View File

@ -208,24 +208,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* MEMORY_BUS_SPEED */ /* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533 #define DDR533_FREQUENCY 266 ///< DDR 533

18
src/mainboard/msi/ms7721/buildOpts.c
View File

@ -207,24 +207,6 @@
// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL }
};
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
/* MEMORY_BUS_SPEED */ /* MEMORY_BUS_SPEED */
#define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR400_FREQUENCY 200 ///< DDR 400
#define DDR533_FREQUENCY 266 ///< DDR 533 #define DDR533_FREQUENCY 266 ///< DDR 533

18
src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h
View File

@ -62,6 +62,22 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
NULL NULL
}; };
/* The default fixed MTRR values to be set after memory initialization */
static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
{ AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
{ AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
{ CPU_LIST_TERMINAL },
};
/* Process solution defined socket / family installations /* Process solution defined socket / family installations
* *
@ -2425,7 +2441,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
#else #else
#define CFG_AP_MTRR_SETTINGS_LIST (NULL) #define CFG_AP_MTRR_SETTINGS_LIST (TrinityApMtrrSettingsList)
#endif #endif
#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST