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mainboard/google/zoombini: Fix some devicetree pci settings 

- Enable I2C #2, #3, and #5
- Enable UART #2
- Enable GSPI #0 and #1
- Disable SATA
- Set pci 1f.0 to chromeec

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.

Change-Id: Ie29652beff36f19a59746a1ad5f8e7f995ef1281
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2017-12-28 20:22:50 -08:00 committed by Martin Roth
parent 2d35ffbf94
commit 7f61fb99d5
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
View File

@ -16,18 +16,18 @@ chip soc/intel/cannonlake
device pci 14.5 on end # SDCard device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0 device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1 device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2 device pci 15.2 on end # I2C #2
device pci 15.3 off end # I2C #3 device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1 device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2 device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on end # SATA device pci 17.0 off end # SATA
device pci 19.0 on end # I2C #4 device pci 19.0 on end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 on end # I2C #5
device pci 19.2 on end # UART #2 device pci 19.2 off end # UART #2
device pci 1a.0 on end # eMMC device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
@ -44,11 +44,11 @@ chip soc/intel/cannonlake
device pci 1d.7 off end # PCI Express Port 16 device pci 1d.7 off end # PCI Express Port 16
device pci 1e.0 on end # UART #0 device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1 device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0 device pci 1e.2 on end # GSPI #0
device pci 1e.3 off end # GSPI #1 device pci 1e.3 on end # GSPI #1
device pci 1f.0 on device pci 1f.0 on
chip drivers/pc80/tpm chip ec/google/chromeec
device pnp 0c31.0 on end device pnp 0c09.0 on end
end end
end # LPC Interface end # LPC Interface
device pci 1f.1 on end # P2SB device pci 1f.1 on end # P2SB