mb/supermicro/x11ssm-f: (re)configure and document various pads
(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:
- GPP_B14: input connected to jumper JBR1 - could be used to implement
"BIOS Recovery" ("Top-Block Swap") functionality; external pull-up
- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
the BMC about a thermal throttling event. Not implemented in vendor
firmware.
- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
Not actively used by vendor firmware.
- GPP_D1: output connected to on-board and front panel power LEDs
- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
be used later in CB:48096 and CB:48097; external pull-up
- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
useful, since the IGD is not connected to any ports on this board.
External pulls ensure correct function of a dGPU even without driving
the gpios. Not used by vendor firmware.
- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls
- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
used by vendor firmware.
Also add comments for documentation. While at it, mark ME-owned pads as
reserved.
Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This commit is contained in:
Michael Niewöhner
parent
5d7fa16c5c
commit
7f623f8e46
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@ -46,26 +46,26 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
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PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE),
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PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
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/* GPIO Group GPP_C */
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// PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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// PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
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/* GPP_C0 - RESERVED */
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/* GPP_C1 - RESERVED */
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PAD_NC(GPP_C2, NONE),
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// PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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// PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* GPP_C3 - RESERVED */
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/* GPP_C4 - RESERVED */
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PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE),
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// PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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// PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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/* GPP_C6 - RESERVED */
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/* GPP_C7 - RESERVED */
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PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF),
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@ -78,14 +78,14 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_C17, NONE),
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_NC(GPP_C20, NONE),
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PAD_CFG_GPO(GPP_C20, 1, PLTRST), /* BMC alert CPU_THROTTLED# */
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PAD_NC(GPP_C21, NONE),
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PAD_CFG_GPI_SMI_LOW(GPP_C22, UP_20K, DEEP, EDGE_SINGLE), /* BMC SMI# */
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PAD_NC(GPP_C23, NONE),
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PAD_CFG_GPI(GPP_C23, NONE, PLTRST), /* CPU CATERR# */
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/* GPIO Group GPP_D */
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PAD_NC(GPP_D0, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), /* Power LEDs onboard + JF1 */
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PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* BMC NMI# */
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PAD_NC(GPP_D3, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE),
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@ -102,11 +102,11 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), /* PERST# CPU PCIe Slots */
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), /* PERST# PCH PCIe Slots */
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PAD_NC(GPP_D20, NONE),
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PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE),
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PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF),
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PAD_CFG_GPI(GPP_D22, NONE, RSMRST), /* BMC enable/disable jumper JPB1 */
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PAD_NC(GPP_D23, NONE),
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/* GPIO Group GPP_E */
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@ -151,10 +151,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE),
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/* GPIO Group GPP_G */
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PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF),
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PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF),
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PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF),
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PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF),
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PAD_NC(GPP_G0, NONE), /* JPCIE6-A19 (DGPU_PWR_EN#) */
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PAD_NC(GPP_G1, NONE), /* JPCIE6-B32 (DGPU_PWR_OK) */
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PAD_NC(GPP_G2, NONE), /* JPCIE6-B30 (DGPU_SEL#) */
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PAD_NC(GPP_G3, NONE), /* JPCIE6-B82 (DGPU_PRSNT#) */
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PAD_NC(GPP_G4, NONE),
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PAD_NC(GPP_G5, NONE),
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PAD_NC(GPP_G6, NONE),
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@ -163,15 +163,15 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_G9, NONE),
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PAD_NC(GPP_G10, NONE),
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PAD_NC(GPP_G11, NONE),
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PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF),
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PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF),
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PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* SKU_ID[0] */
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PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* SKU_ID[1] */
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PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */
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PAD_CFG_GPI(GPP_G15, NONE, PLTRST), /* SKU_ID[3] */
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PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* SKU_ID[4] */
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PAD_NC(GPP_G17, NONE),
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PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */
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PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */
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PAD_NC(GPP_G20, NONE),
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PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */
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PAD_NC(GPP_G21, NONE),
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PAD_NC(GPP_G22, NONE),
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PAD_NC(GPP_G23, NONE),
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