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Michael Niewöhner 7f623f8e46 mb/supermicro/x11ssm-f: (re)configure and document various pads
(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:

- GPP_B14: input connected to jumper JBR1 - could be used to implement
  "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up

- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
  the BMC about a thermal throttling event. Not implemented in vendor
  firmware.

- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
  Not actively used by vendor firmware.

- GPP_D1: output connected to on-board and front panel power LEDs

- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
  used for testing/debugging only, since it resets both slots at once.
  Not actively used by vendor firmware.

- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
  be used later in CB:48096 and CB:48097; external pull-up

- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
  useful, since the IGD is not connected to any ports on this board.
  External pulls ensure correct function of a dGPU even without driving
  the gpios. Not used by vendor firmware.

- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls

- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
  used by vendor firmware.

Also add comments for documentation. While at it, mark ME-owned pads as
reserved.

Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-10 02:25:13 +00:00
3rdparty 3rdparty/amd_blobs: Update pointer for picasso SMU and FSP 2020-12-02 15:20:35 +00:00
Documentation Documentation/mainboard/ocp: Update DeltaLake 2020-12-05 09:47:00 +00:00
LICENSES
configs configs: Add a sample config for scaleway tagada 2020-11-20 00:45:37 +00:00
payloads coreboot tables: Add SPI flash memory map windows to coreboot tables 2020-12-08 22:56:09 +00:00
src mb/supermicro/x11ssm-f: (re)configure and document various pads 2020-12-10 02:25:13 +00:00
tests edist-test: Fix _Static_assert missing message string 2020-12-02 10:38:25 +00:00
util util/cbfstool/fmaptool: Generate list of terminal sections 2020-12-08 18:59:05 +00:00
.checkpatch.conf
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules
.gitreview
AUTHORS
COPYING
MAINTAINERS MAINTAINERS: add maintainers for AMD family 17h and 19h reference boards 2020-12-08 14:53:55 +00:00
Makefile Makefile: Remove possibly illegal characters from doxyplatform 2020-10-31 18:21:06 +00:00
Makefile.inc Makefile.inc: Fix empty output when processing C struct files in CBFS 2020-12-09 23:18:10 +00:00
README.md
gnat.adc
toolchain.inc

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.