arch/x86: introduce postcar stage/phase
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
parent
2b23948535
commit
7f8afe0631
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@ -84,7 +84,7 @@ subdirs-y += site-local
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#######################################################################
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# Add source classes and their build options
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classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage verstage
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classes-y := ramstage romstage bootblock postcar smm smmstub cpu_microcode libverstage verstage
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# Add dynamic classes for rmodules
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$(foreach supported_arch,$(ARCH_SUPPORTED), \
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@ -167,3 +167,8 @@ config ROMSTAGE_ADDR
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config VERSTAGE_ADDR
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hex
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default 0x2000000
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# Use the post CAR infrastructure for tearing down cache-as-ram
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# from a program loaded in ram and subsequently loading ramstage.
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config POSTCAR_STAGE
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def_bool n
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@ -331,6 +331,7 @@ endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
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ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
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romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c
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romstage-y += cbmem.c
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romstage-y += boot.c
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@ -390,3 +391,27 @@ rmodules_x86_64-y += memmove.c
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endif
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endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
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$(eval $(call create_class_compiler,postcar,x86_32))
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postcar-generic-ccopts += -D__POSTCAR__
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postcar-y += boot.c
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postcar-y += cbfs_and_run.c
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postcar-y += exit_car.S
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postcar-y += memset.c
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postcar-y += memcpy.c
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postcar-y += memmove.c
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postcar-y += memlayout.ld
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postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
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$(objcbfs)/postcar.debug: $$(postcar-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld)
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$(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod
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cp $< $@
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cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar
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$(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf
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$(CONFIG_CBFS_PREFIX)/postcar-type := stage
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$(CONFIG_CBFS_PREFIX)/postcar-compression := none
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@ -0,0 +1,106 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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.section ".module_parameters", "aw", @progbits
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/* stack_top indicates the stack to pull MTRR information from. */
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stack_top:
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.long 0
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.long 0
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.text
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.global _start
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_start:
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/* chipset_teardown_car() is expected to disable cache-as-ram. */
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call chipset_teardown_car
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/* Enable caching if not already enabled. */
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mov %cr0, %eax
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and $(~(CR0_CD | CR0_NW)), %eax
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mov %eax, %cr0
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/* Ensure cache is clean. */
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invd
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/* Set up new stack. */
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mov stack_top, %esp
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/*
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* Honor variable MTRR information pushed on the stack with the
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* following layout:
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*
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* Offset: Value
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* ...
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* 0x14: MTRR mask 0 63:32
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* 0x10: MTRR mask 0 31:0
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* 0x0c: MTRR base 0 63:32
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* 0x08: MTRR base 0 31:0
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* 0x04: Number of variable MTRRs to set
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* 0x00: Number of variable MTRRs to clear
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*/
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/* Clear variable MTRRs. */
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pop %ebx /* Number to clear */
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test %ebx, %ebx
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jz 2f
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xor %eax, %eax
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xor %edx, %edx
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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2:
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/* Set Variable MTRRs based on stack contents. */
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pop %ebx /* Number to set. */
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test %ebx, %ebx
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jz 2f
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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/* Write MTRR base. */
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pop %eax
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pop %edx
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wrmsr
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inc %ecx
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/* Write MTRR mask. */
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pop %eax
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pop %edx
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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2:
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/* Enable MTRR. */
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mov $(MTRR_DEF_TYPE_MSR), %ecx
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rdmsr
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/* Make default type uncacheable. */
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and $(~(MTRR_DEF_TYPE_MASK)), %eax
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or $(MTRR_DEF_TYPE_EN), %eax
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wrmsr
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/* Load and run ramstage. */
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call copy_and_run
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/* Should never return. */
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1:
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jmp 1b
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@ -15,6 +15,7 @@
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#define ARCH_CPU_H
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#include <stdint.h>
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#include <stddef.h>
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#include <rules.h>
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/*
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@ -246,6 +247,42 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
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* cache-as-ram.
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*/
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void asmlinkage car_stage_entry(void);
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/*
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* Support setting up a stack frame consisting of MTRR information
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* for use in bootstrapping the caching attributes after cache-as-ram
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* is torn down.
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*/
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struct postcar_frame {
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uintptr_t stack;
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uint32_t upper_mask;
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int max_var_mttrs;
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int num_var_mttrs;
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};
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/*
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* Initialize postcar_frame object allocating stack size in cbmem
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* with the provided size. Returns 0 on success, < 0 on error.
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*/
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int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
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/*
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* Add variable MTRR covering the provided range with MTRR type.
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*/
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void postcar_frame_add_mtrr(struct postcar_frame *pcf,
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uintptr_t addr, size_t size, int type);
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/*
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* Load and run a program that takes control of execution that
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* tears down CAR and loads ramstage. The postcar_frame object
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* indicates how to set up the frame. If caching is enabled at
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* the time of the call it is up to the platform code to handle
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* coherency with dirty lines in the cache using some mechansim
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* such as platform_prog_run() because run_postcar_phase()
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* utilizes prog_run() internally.
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*/
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void run_postcar_phase(struct postcar_frame *pcf);
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#endif
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#endif /* ARCH_CPU_H */
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@ -51,6 +51,8 @@ SECTIONS
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/* Pull in the cache-as-ram rules. */
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#include "car.ld"
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#elif ENV_POSTCAR
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POSTCAR(32M, 1M)
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#endif
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}
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@ -0,0 +1,115 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include <rmodule.h>
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static inline void stack_push(struct postcar_frame *pcf, uint32_t val)
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{
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uint32_t *ptr;
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pcf->stack -= sizeof(val);
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ptr = (void *)pcf->stack;
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*ptr = val;
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}
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int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
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{
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void *stack;
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msr_t msr;
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msr = rdmsr(MTRR_CAP_MSR);
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stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size);
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if (stack == NULL) {
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printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n",
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stack_size);
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return -1;
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}
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pcf->stack = (uintptr_t)stack;
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pcf->stack += stack_size;
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pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1;
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pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT;
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pcf->num_var_mttrs = 0;
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return 0;
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}
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void postcar_frame_add_mtrr(struct postcar_frame *pcf,
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uintptr_t addr, size_t size, int type)
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{
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size_t align;
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if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
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printk(BIOS_ERR, "No more variable MTRRs: %d\n",
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pcf->max_var_mttrs);
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return;
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}
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/* Determine address alignment by lowest bit set in address. */
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align = addr & (addr ^ (addr - 1));
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if (align < size) {
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printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
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addr, align, size);
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size = align;
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}
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/* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
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stack_push(pcf, pcf->upper_mask);
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stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
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stack_push(pcf, 0);
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stack_push(pcf, addr | type);
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pcf->num_var_mttrs++;
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}
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void run_postcar_phase(struct postcar_frame *pcf)
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{
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struct prog prog =
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PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar");
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struct rmod_stage_load rsl = {
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.cbmem_id = CBMEM_ID_AFTER_CAR,
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.prog = &prog,
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};
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/*
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* Place the number of used variable MTRRs on stack then max number
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* of variable MTRRs supported in the system.
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*/
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stack_push(pcf, pcf->num_var_mttrs);
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stack_push(pcf, pcf->max_var_mttrs);
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if (prog_locate(&prog))
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die("Failed to locate after CAR program.\n");
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if (rmodule_stage_load(&rsl))
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die("Failed to load after CAR program.\n");
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/* Set the stack pointer within parameters of the program loaded. */
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if (rsl.params == NULL)
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die("No parameters found in after CAR program.\n");
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*(uintptr_t *)rsl.params = pcf->stack;
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prog_run(&prog);
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}
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@ -2,12 +2,14 @@ bootblock-y += mem_pool.c
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verstage-y += mem_pool.c
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romstage-y += mem_pool.c
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ramstage-y += mem_pool.c
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postcar-y += mem_pool.c
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bootblock-y += region.c
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verstage-y += region.c
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romstage-y += region.c
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ramstage-y += region.c
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smm-y += region.c
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postcar-y += region.c
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ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c
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@ -16,8 +18,10 @@ verstage-y += cbfs.c
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romstage-y += cbfs.c
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ramstage-y += cbfs.c
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smm-y += cbfs.c
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postcar-y += cbfs.c
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bootblock-y += lz4_wrapper.c
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verstage-y += lz4_wrapper.c
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romstage-y += lz4_wrapper.c
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ramstage-y += lz4_wrapper.c
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postcar-y += lz4_wrapper.c
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@ -20,6 +20,7 @@
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#define CBMEM_ID_ACPI 0x41435049
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#define CBMEM_ID_ACPI_GNVS 0x474e5653
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#define CBMEM_ID_ACPI_GNVS_PTR 0x474e5650
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#define CBMEM_ID_AFTER_CAR 0xc4787a93
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#define CBMEM_ID_AGESA_RUNTIME 0x41474553
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#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
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#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3
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@ -71,6 +72,7 @@
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{ CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \
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{ CBMEM_ID_ACPI_GNVS_PTR, "GNVS PTR " }, \
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{ CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \
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{ CBMEM_ID_AFTER_CAR, "AFTER CAR" }, \
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{ CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \
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{ CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \
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{ CBMEM_ID_CBTABLE, "COREBOOT " }, \
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@ -18,6 +18,11 @@ romstage-y += init.c console.c
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romstage-y += post.c
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romstage-y += die.c
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postcar-y += vtxprintf.c printk.c
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postcar-y += init.c console.c
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postcar-y += post.c
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postcar-y += die.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c
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bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c
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bootblock-y += die.c
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@ -7,3 +7,4 @@ bootblock-y += boot_cpu.c
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verstage-y += boot_cpu.c
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romstage-y += boot_cpu.c
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ramstage-y += boot_cpu.c
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postcar-y += boot_cpu.c
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@ -47,7 +47,7 @@ void __attribute__ ((noreturn)) die(const char *msg);
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#define __CONSOLE_ENABLE__ \
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((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || \
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ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \
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ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR || \
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(ENV_SMM && CONFIG_DEBUG_SMI))
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#if __CONSOLE_ENABLE__
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@ -160,6 +160,18 @@
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#define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size)
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#endif
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#if ENV_POSTCAR
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#define POSTCAR(addr, sz) \
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SYMBOL(postcar, addr) \
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_epostcar = _postcar + sz; \
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_ = ASSERT(_eprogram - _program <= sz, \
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STR(Aftercar exceeded its allotted size! (sz))); \
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INCLUDE "postcar/lib/program.ld"
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#else
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#define POSTCAR(addr, sz) \
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REGION(postcar, addr, sz, 1)
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#endif
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#define WATCHDOG_TOMBSTONE(addr, size) \
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REGION(watchdog_tombstone, addr, size, 4) \
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_ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!");
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@ -26,6 +26,7 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "bootblock"
|
||||
|
||||
#elif defined(__ROMSTAGE__)
|
||||
|
|
@ -35,6 +36,7 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "romstage"
|
||||
|
||||
#elif defined(__SMM__)
|
||||
|
|
@ -44,6 +46,7 @@
|
|||
#define ENV_SMM 1
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "smm"
|
||||
|
||||
#elif defined(__VERSTAGE__)
|
||||
|
|
@ -53,6 +56,7 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 1
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "verstage"
|
||||
|
||||
#elif defined(__RAMSTAGE__)
|
||||
|
|
@ -62,6 +66,7 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "ramstage"
|
||||
|
||||
#elif defined(__RMODULE__)
|
||||
|
|
@ -71,8 +76,19 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 1
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "rmodule"
|
||||
|
||||
#elif defined(__POSTCAR__)
|
||||
#define ENV_BOOTBLOCK 0
|
||||
#define ENV_ROMSTAGE 0
|
||||
#define ENV_RAMSTAGE 0
|
||||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 1
|
||||
#define ENV_STRING "postcar"
|
||||
|
||||
#else
|
||||
/*
|
||||
* Default case of nothing set for random blob generation using
|
||||
|
|
@ -86,18 +102,21 @@
|
|||
#define ENV_SMM 0
|
||||
#define ENV_VERSTAGE 0
|
||||
#define ENV_RMODULE 0
|
||||
#define ENV_POSTCAR 0
|
||||
#define ENV_STRING "UNKNOWN"
|
||||
#endif
|
||||
|
||||
/* For romstage and ramstage always build with simple device model, ie.
|
||||
* PCI, PNP and CPU functions operate without use of devicetree.
|
||||
/* For pre-DRAM stages and post-CAR always build with simple device model, ie.
|
||||
* PCI, PNP and CPU functions operate without use of devicetree. The reason
|
||||
* post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's
|
||||
* no known requirement that devicetree would be needed during that stage.
|
||||
*
|
||||
* For ramstage individual source file may define __SIMPLE_DEVICE__
|
||||
* before including any header files to force that particular source
|
||||
* be built with simple device model.
|
||||
*/
|
||||
|
||||
#if defined(__PRE_RAM__) || defined(__SMM__)
|
||||
#if defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR
|
||||
#define __SIMPLE_DEVICE__
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -131,13 +131,16 @@ ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c
|
|||
|
||||
romstage-y += cbmem_common.c
|
||||
romstage-y += imd_cbmem.c
|
||||
romstage-y += imd.c
|
||||
|
||||
ramstage-y += cbmem_common.c
|
||||
ramstage-y += imd_cbmem.c
|
||||
|
||||
romstage-y += imd.c
|
||||
ramstage-y += imd.c
|
||||
|
||||
postcar-y += cbmem_common.c
|
||||
postcar-y += imd_cbmem.c
|
||||
postcar-y += imd.c
|
||||
|
||||
bootblock-y += hexdump.c
|
||||
ramstage-y += hexdump.c
|
||||
romstage-y += hexdump.c
|
||||
|
|
@ -167,12 +170,14 @@ romstage-y += version.c
|
|||
ramstage-y += version.c
|
||||
smm-y += version.c
|
||||
verstage-y += version.c
|
||||
postcar-y += version.c
|
||||
|
||||
$(call src-to-obj,bootblock,$(dir)/version.c) : $(obj)/build.h
|
||||
$(call src-to-obj,romstage,$(dir)/version.c) : $(obj)/build.h
|
||||
$(call src-to-obj,ramstage,$(dir)/version.c) : $(obj)/build.h
|
||||
$(call src-to-obj,smm,$(dir)/version.c) : $(obj)/build.h
|
||||
$(call src-to-obj,verstage,$(dir)/version.c) : $(obj)/build.h
|
||||
$(call src-to-obj,postcar,$(dir)/version.c) : $(obj)/build.h
|
||||
|
||||
romstage-y += bootmode.c
|
||||
ramstage-y += bootmode.c
|
||||
|
|
@ -183,9 +188,27 @@ romstage-y += halt.c
|
|||
ramstage-y += halt.c
|
||||
smm-y += halt.c
|
||||
|
||||
postcar-y += bootmode.c
|
||||
postcar-y += boot_device.c
|
||||
postcar-y += cbfs.c
|
||||
postcar-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c
|
||||
postcar-y += delay.c
|
||||
postcar-y += fmap.c
|
||||
postcar-y += gcc.c
|
||||
postcar-y += halt.c
|
||||
postcar-y += libgcc.c
|
||||
postcar-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c
|
||||
postcar-y += memchr.c
|
||||
postcar-y += memcmp.c
|
||||
postcar-y += prog_loaders.c
|
||||
postcar-y += prog_ops.c
|
||||
postcar-y += rmodule.c
|
||||
postcar-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
|
||||
|
||||
# Use program.ld for all the platforms which use C fo the bootblock.
|
||||
bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += program.ld
|
||||
|
||||
postcar-y += program.ld
|
||||
romstage-y += program.ld
|
||||
ramstage-y += program.ld
|
||||
verstage-y += program.ld
|
||||
|
|
|
|||
|
|
@ -80,7 +80,14 @@
|
|||
. = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
|
||||
_data = .;
|
||||
|
||||
#if ENV_RMODULE
|
||||
/*
|
||||
* The postcar phase uses a stack value that is located in the relocatable
|
||||
* module section. While the postcar stage could be linked like smm and
|
||||
* other rmodules the postcar stage needs similar semantics of the more
|
||||
* traditional stages in the coreboot infrastructure. Therefore it's easier
|
||||
* to specialize this case.
|
||||
*/
|
||||
#if ENV_RMODULE || ENV_POSTCAR
|
||||
_rmodule_params = .;
|
||||
KEEP(*(.module_parameters));
|
||||
_ermodule_params = .;
|
||||
|
|
|
|||
Loading…
Reference in New Issue