7f8afe0631
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
106 lines
2.1 KiB
ArmAsm
106 lines
2.1 KiB
ArmAsm
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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.section ".module_parameters", "aw", @progbits
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/* stack_top indicates the stack to pull MTRR information from. */
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stack_top:
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.long 0
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.long 0
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.text
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.global _start
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_start:
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/* chipset_teardown_car() is expected to disable cache-as-ram. */
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call chipset_teardown_car
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/* Enable caching if not already enabled. */
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mov %cr0, %eax
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and $(~(CR0_CD | CR0_NW)), %eax
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mov %eax, %cr0
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/* Ensure cache is clean. */
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invd
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/* Set up new stack. */
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mov stack_top, %esp
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/*
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* Honor variable MTRR information pushed on the stack with the
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* following layout:
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*
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* Offset: Value
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* ...
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* 0x14: MTRR mask 0 63:32
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* 0x10: MTRR mask 0 31:0
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* 0x0c: MTRR base 0 63:32
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* 0x08: MTRR base 0 31:0
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* 0x04: Number of variable MTRRs to set
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* 0x00: Number of variable MTRRs to clear
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*/
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/* Clear variable MTRRs. */
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pop %ebx /* Number to clear */
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test %ebx, %ebx
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jz 2f
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xor %eax, %eax
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xor %edx, %edx
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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wrmsr
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inc %ecx
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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2:
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/* Set Variable MTRRs based on stack contents. */
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pop %ebx /* Number to set. */
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test %ebx, %ebx
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jz 2f
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mov $(MTRR_PHYS_BASE(0)), %ecx
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1:
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/* Write MTRR base. */
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pop %eax
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pop %edx
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wrmsr
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inc %ecx
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/* Write MTRR mask. */
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pop %eax
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pop %edx
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wrmsr
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inc %ecx
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dec %ebx
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jnz 1b
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2:
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/* Enable MTRR. */
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mov $(MTRR_DEF_TYPE_MSR), %ecx
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rdmsr
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/* Make default type uncacheable. */
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and $(~(MTRR_DEF_TYPE_MASK)), %eax
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or $(MTRR_DEF_TYPE_EN), %eax
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wrmsr
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/* Load and run ramstage. */
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call copy_and_run
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/* Should never return. */
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1:
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jmp 1b
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