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mb/intel/mtlrvp: Add configuration for UART devices 

This patch adds below configuration for MTL-RVP UART devices,
Interface -> UART0
PCI -> 0:0x1e:0
Device -> AP UART

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp ito chromeOS
using subsequent patches in the train. UART logs appear on AP console.

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Harsha B R 2022-12-16 12:47:55 +05:30 committed by Eric Lai
parent ec0a85b580
commit 7fb5bf8893
2 changed files with 14 additions and 0 deletions
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8
src/mainboard/intel/mtlrvp/Kconfig
View File

@ -22,6 +22,10 @@ config CHROMEOS
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE select HAS_RECOVERY_MRC_CACHE
config BOARD_SPECIFIC_OPTIONS
def_bool y
select INTEL_LPSS_UART_FOR_CONSOLE
config MAINBOARD_DIR config MAINBOARD_DIR
default "intel/mtlrvp" default "intel/mtlrvp"
@ -81,4 +85,8 @@ endchoice
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
config UART_FOR_CONSOLE
int
default 0
endif # BOARD_INTEL_MTLRVP_COMMON endif # BOARD_INTEL_MTLRVP_COMMON

6
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -11,6 +11,12 @@ chip soc/intel/meteorlake
# EC memory map range is 0x900-0x9ff # EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901" register "gen3_dec" = "0x00fc0901"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
device domain 0 on device domain 0 on
device ref igpu on end device ref igpu on end
device ref heci1 on end device ref heci1 on end