util/inteltool: Add ICH6-10 to BIOS_CNTL list
Without this change inteltool cannot read BIOS_CNTL values nor can it read the SPIBAR values. Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17979 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -3,6 +3,20 @@
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#include <stdlib.h>
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#include "inteltool.h"
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static const io_register_t ich6_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 6, "reserved" },
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};
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static const io_register_t ich7_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 2, "SPI Read configuration" },
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{ 0x4, 1, "TopSwapStatus" },
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{ 0x5, 3, "reserved" },
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};
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static const io_register_t pch_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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@ -74,6 +88,30 @@ int print_bioscntl(struct pci_dev *sb)
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printf("\n============= SPI / BIOS CNTL =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH6:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = ich6_bios_cntl_registers;
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size = ARRAY_SIZE(ich6_bios_cntl_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH8ME:
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case PCI_DEVICE_ID_INTEL_ICH9DH:
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case PCI_DEVICE_ID_INTEL_ICH9DO:
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case PCI_DEVICE_ID_INTEL_ICH9R:
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case PCI_DEVICE_ID_INTEL_ICH9:
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case PCI_DEVICE_ID_INTEL_ICH9M:
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case PCI_DEVICE_ID_INTEL_ICH9ME:
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = ich7_bios_cntl_registers;
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size = ARRAY_SIZE(ich7_bios_cntl_registers);
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break;
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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