get solo building after last infrastructure changes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -4,7 +4,8 @@
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/smp/lapic.h>
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#include <cpu/x86/lapic.h>
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#include <arch/cpu.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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@ -13,13 +14,15 @@
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "superio/NSC/pc87360/pc87360_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
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@ -90,7 +93,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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static void main(void)
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static void main(unsigned long bist)
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{
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static const struct mem_controller cpu[] = {
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{
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@ -105,23 +108,34 @@ static void main(void)
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};
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int needs_reset;
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if (bist == 0) {
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/* Skip this if there was a built in self test failure */
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amd_early_mtrr_init();
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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asm volatile ("jmp __cpu_reset");
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}
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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print_err("This LinuxBIOS image is built for UP only.\n");
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/* This LinuxBIOS image is built for UP only */
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stop_this_cpu();
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}
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}
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/* Setup the console */
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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@ -133,9 +147,7 @@ static void main(void)
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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@ -146,8 +158,8 @@ static void main(void)
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#if 0
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dump_pci_devices();
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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/* Check the first 1M */
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ram_check(0x00000000, 0x000100000);
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#endif
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}
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@ -1,4 +1,4 @@
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extern struct chip_operations mainboard_amd_solo_control;
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extern struct chip_operations mainboard_amd_solo_ops;
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struct mainboard_amd_solo_config {
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int nothing;
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@ -9,7 +9,26 @@
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#include "../../../northbridge/amd/amdk8/northbridge.h"
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#include "chip.h"
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static void mainboard_init(device_t dev)
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{
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root_dev_init(dev);
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}
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struct chip_operations mainboard_amd_solo_control = {
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.name = "AMD Solo7 mainboard ",
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = root_dev_enable_resources,
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.init = mainboard_init,
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.scan_bus = root_dev_scan_bus,
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.enable = 0,
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};
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static void enable_dev(struct device *dev)
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{
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dev->ops = &mainboard_operations;
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}
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struct chip_operations mainboard_amd_solo_ops = {
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.name = "AMD Solo7 mainboard ",
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.enable_dev = enable_dev,
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};
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@ -4,7 +4,7 @@
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#include <string.h>
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#include <stdint.h>
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void *smp_write_config_table(void *v, unsigned long *processor_map)
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "AMD ";
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@ -32,7 +32,7 @@ void *smp_write_config_table(void *v, unsigned long *processor_map)
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc, processor_map);
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smp_write_processors(mc);
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{
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device_t dev;
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@ -233,10 +233,9 @@ void *smp_write_config_table(void *v, unsigned long *processor_map)
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr,
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unsigned long *processor_map)
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long) smp_write_config_table(v, processor_map);
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return (unsigned long) smp_write_config_table(v);
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}
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