cpu/amd,intel/*/Makefile: don't add cpu/x86/cache

Some CPUs don't use the ramstage-only x86_enable_cache helper function
to call enable_cache with some added port 0x80 and console output.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ia44c7b150cd12d76e463903966f67d86750cbdd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/cpu/amd/pi/00730F01/Makefile.inc

@@ -9,4 +9,3 @@ ramstage-y += update_microcode.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache

src/cpu/intel/haswell/Makefile.inc

@@ -16,7 +16,6 @@ bootblock-y += bootblock.c
 postcar-y += ../car/non-evict/exit_car.S
 
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

src/cpu/intel/model_2065x/Makefile.inc

@@ -1,6 +1,5 @@
 ramstage-y += model_2065x_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/lapic
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode

src/cpu/intel/model_206ax/Makefile.inc

@@ -3,7 +3,6 @@ subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../turbo