device/dram/ddr2: Use 'enum cb_err' instead of 'int'
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/68240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -122,7 +122,7 @@ u8 spd_get_msbs(u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th ns.
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* Returns cycle time in 1/256th ns.
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*/
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*/
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static int spd_decode_tck_time(u32 *tck, u8 c)
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static enum cb_err spd_decode_tck_time(u32 *tck, u8 c)
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{
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{
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u8 high, low;
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u8 high, low;
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@ -159,7 +159,7 @@ static int spd_decode_tck_time(u32 *tck, u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th ns.
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* Returns cycle time in 1/256th ns.
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*/
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*/
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static int spd_decode_bcd_time(u32 *bcd, u8 c)
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static enum cb_err spd_decode_bcd_time(u32 *bcd, u8 c)
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{
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{
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u8 high, low;
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u8 high, low;
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@ -194,7 +194,7 @@ static u32 spd_decode_quarter_time(u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th us.
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* Returns cycle time in 1/256th us.
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*/
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*/
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static int spd_decode_tRR_time(u32 *tRR, u8 c)
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static enum cb_err spd_decode_tRR_time(u32 *tRR, u8 c)
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{
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{
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switch (c & ~0x80) {
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switch (c & ~0x80) {
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default:
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default:
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