src/soc: Fix typo
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -156,7 +156,7 @@ struct soc_intel_cannonlake_config {
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/* PCIe ouput clocks type to Pcie devices.
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/* PCIe output clocks type to Pcie devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS];
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@ -116,7 +116,7 @@ struct soc_intel_skylake_config {
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/* Estimated maximum platform power in Watts */
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u16 psys_pmax;
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/* Wether to ignore VT-d support of the SKU */
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/* Whether to ignore VT-d support of the SKU */
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int ignore_vtd;
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/*
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@ -88,7 +88,7 @@ struct soc_nvidia_tegra124_config {
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int pixel_clock;
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/* The minimum link configuraton settings */
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/* The minimum link configuration settings */
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u32 lane_count;
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u32 enhanced_framing;
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u32 link_bw;
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@ -23,7 +23,7 @@
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#include <stdlib.h>
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/*
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* This function reads SDRAM parameters (and a few CLK_RST regsiter values) from
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* This function reads SDRAM parameters (and a few CLK_RST register values) from
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* the common BCT format and writes them into PMC scratch registers (where the
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* BootROM expects them on LP0 resume). Since those store the same values in a
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* different format, we follow a "translation table" taken from Nvidia's U-Boot
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@ -76,7 +76,7 @@ struct soc_nvidia_tegra210_config {
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int hpd_plug_min_us;
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int hpd_irq_min_us;
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/* The minimum link configuraton settings */
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/* The minimum link configuration settings */
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u32 lane_count;
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u32 enhanced_framing;
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u32 link_bw;
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@ -329,7 +329,7 @@ void uart_init(int idx)
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GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
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write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
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/* Intialize UART_DM */
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/* Initialize UART_DM */
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msm_boot_uart_dm_init(dm_base);
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}
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@ -469,7 +469,7 @@ void rkclk_configure_i2s(unsigned int hz)
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/* i2s source clock: gpll
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i2s0_outclk_sel: clk_i2s
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i2s0_clk_sel: divider ouput from fraction
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i2s0_clk_sel: divider output from fraction
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i2s0_pll_div_con: 0*/
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write32(&cru_ptr->cru_clksel_con[4],
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RK_CLRSETBITS(1 << 15 | 1 << 12 | 3 << 8 | 0x7f << 0,
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@ -804,7 +804,7 @@ void rkclk_configure_i2s(unsigned int hz)
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int v;
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/**
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* clk_i2s0_sel: divider ouput from fraction
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* clk_i2s0_sel: divider output from fraction
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* clk_i2s0_pll_sel source clock: cpll
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* clk_i2s0_div_con: 1 (div+1)
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*/
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