intel post-car: Split legacy sockets

Move old sockets to use romstage_legacy.c, these are ones
using intel/car/cache_as_ram.inc.

These will not be converted to RELOCATABLE_RAMSTAGE as boards
are candidates for getting dropped from the tree anyways.

Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-27 13:24:11 +03:00
parent 19652e6f40
commit 8160a2f63d
6 changed files with 25 additions and 5 deletions

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@ -0,0 +1,20 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/intel/romstage.h>
void * asmlinkage romstage_main(unsigned long bist)
{
mainboard_romstage_entry(bist);
return (void*)CONFIG_RAMTOP;
}

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@ -29,4 +29,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage.c
romstage-y += ../car/romstage_legacy.c

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@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage.c
romstage-y += ../car/romstage_legacy.c

View File

@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage.c
romstage-y += ../car/romstage_legacy.c

View File

@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage.c
romstage-y += ../car/romstage_legacy.c

View File

@ -10,4 +10,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage.c
romstage-y += ../car/romstage_legacy.c