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intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC 

Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2023-04-08 09:43:56 +03:00
parent 7f8e2a6a4a
commit 81dc352032
6 changed files with 3 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/broadwell/pch/Kconfig
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@ -4,6 +4,7 @@ config INTEL_LYNXPOINT_LP
config PCH_SPECIFIC_OPTIONS config PCH_SPECIFIC_OPTIONS
def_bool y def_bool y
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_SOC_NVS select ACPI_SOC_NVS
@ -17,7 +18,6 @@ config PCH_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_LYNXPOINT_LP select INTEL_LYNXPOINT_LP
select RTC select RTC
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RTC

2
src/southbridge/intel/bd82x6x/Kconfig
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@ -10,6 +10,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
config SOUTH_BRIDGE_OPTIONS config SOUTH_BRIDGE_OPTIONS
def_bool y def_bool y
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_SOC_NVS select ACPI_SOC_NVS
@ -34,7 +35,6 @@ config SOUTH_BRIDGE_OPTIONS
select RTC select RTC
select HAVE_INTEL_CHIPSET_LOCKDOWN select HAVE_INTEL_CHIPSET_LOCKDOWN
select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_SMM
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
select TCO_SPACE_NOT_YET_SPLIT select TCO_SPACE_NOT_YET_SPLIT

3
src/southbridge/intel/common/Kconfig.common
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@ -61,9 +61,6 @@ config SOUTHBRIDGE_INTEL_COMMON_SMM
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMBASE
config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
bool
config SOUTHBRIDGE_INTEL_COMMON_FINALIZE config SOUTHBRIDGE_INTEL_COMMON_FINALIZE
bool bool

2
src/southbridge/intel/common/Makefile.inc
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@ -50,8 +50,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ) += rcba_pirq.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smi.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM) += pmutil.c smihandler.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT) += madt.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c

19
src/southbridge/intel/common/madt.c
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@ -1,19 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
unsigned long acpi_fill_madt(unsigned long current)
{
/* IOAPIC */
current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
return current;
}

2
src/southbridge/intel/lynxpoint/Kconfig
View File

@ -7,6 +7,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT
config SOUTH_BRIDGE_OPTIONS config SOUTH_BRIDGE_OPTIONS
def_bool y def_bool y
select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_SOC_NVS select ACPI_SOC_NVS
@ -14,7 +15,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_FINALIZE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_PMBASE