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mb/google/brya: Add RTD3 for WWAN 

Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 6 and provide the reset GPIO / src clk pins.

BUG=None
BRANCH=None
TEST=Build and boot the coreboot image, check if device is enumerated
in the lspci list after warm/cold reboot cycles, run suspend cycles and
check if WWAN is entering L2 LPM.

Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: Ie9d1ce55cc1297ea0e1069979bbecfaac8f8de05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Thejaswani Putta 2021-07-30 12:38:37 -07:00 committed by Tim Wawrzynczak
parent e8cd480046
commit 8239d076bf
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
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@ -140,6 +140,11 @@ chip soc/intel/alderlake
device ref sata on end device ref sata on end
device ref pcie_rp6 on device ref pcie_rp6 on
# Enable WWAN PCIE 6 using clk 5 # Enable WWAN PCIE 6 using clk 5
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
register "srcclk_pin" = "5"
device generic 0 on end
end
register "pch_pcie_rp[PCH_RP(6)]" = "{ register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5, .clk_src = 5,
.clk_req = 5, .clk_req = 5,