intel/haswell: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -7,12 +7,8 @@ romstage-y += ../car/romstage.c
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postcar-y += tsc_freq.c
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ramstage-y += acpi.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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smm-y += finalize.c
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smm-y += tsc_freq.c
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@ -118,15 +118,9 @@
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/* Data is passed through bits 31:0 of the data register. */
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#define BIOS_MAILBOX_DATA 0x5da0
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE)
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/* Sanity check config options. */
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE))
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)"
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#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
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# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
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#endif
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#if (CONFIG_SMM_TSEG_SIZE < 0x800000)
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# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
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@ -250,7 +250,7 @@ static void fill_in_relocation_params(struct device *dev,
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params->ied_size = tseg_size - params->smram_size;
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/* Adjust available SMM handler memory size. */
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params->smram_size -= RESERVED_SMM_SIZE;
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params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
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/* SMRR has 32-bits of valid address aligned to 4KiB. */
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params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
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@ -1,26 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <stage_cache.h>
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#include "haswell.h"
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address. */
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*size = RESERVED_SMM_SIZE;
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*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
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}
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@ -18,6 +18,7 @@
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <stage_cache.h>
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#include "haswell.h"
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static uintptr_t smm_region_start(void)
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@ -34,3 +35,16 @@ void *cbmem_top(void)
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{
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return (void *)smm_region_start();
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}
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/* Region of SMM space is reserved for multipurpose use. It falls below
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* the IED region and above the SMM handler. */
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#define RESERVED_SMM_OFFSET \
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(CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE)
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address. */
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
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}
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