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device/oprom: Reduce indentation 

Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-07-04 06:12:55 +03:00
parent b28b6b53cc
commit 8261d67ae7
1 changed files with 101 additions and 94 deletions
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195
src/device/oprom/yabel/io.c
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@ -410,66 +410,69 @@ my_outl(X86EMU_pioAddr addr, u32 val)
u32 u32
pci_cfg_read(X86EMU_pioAddr addr, u8 size) pci_cfg_read(X86EMU_pioAddr addr, u8 size)
{ {
u32 port_cf8_val = 0;
u32 rval = 0xFFFFFFFF; u32 rval = 0xFFFFFFFF;
struct device * dev; struct device *dev = NULL;
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { u8 bus, devfn, offs;
// PCI Configuration Mechanism 1 step 1
// write to 0xCF8, sets bus, device, function and Config Space offset // PCI Configuration Mechanism 1 step 1
// later read from 0xCFC-0xCFF returns the value... // write to 0xCF8, sets bus, device, function and Config Space offset
u8 bus, devfn, offs; // later read from 0xCFC-0xCFF returns the value...
u32 port_cf8_val = my_inl(0xCF8); if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
if ((port_cf8_val & 0x80000000) != 0) { port_cf8_val = my_inl(0xCF8);
//highest bit enables config space mapping
bus = (port_cf8_val & 0x00FF0000) >> 16; if ((port_cf8_val & 0x80000000) == 0)
devfn = (port_cf8_val & 0x0000FF00) >> 8; return rval;
offs = (port_cf8_val & 0x000000FF);
offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly //highest bit enables config space mapping
DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n", bus = (port_cf8_val & 0x00FF0000) >> 16;
__func__, bus, devfn, offs); devfn = (port_cf8_val & 0x0000FF00) >> 8;
offs = (port_cf8_val & 0x000000FF);
offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
__func__, bus, devfn, offs);
#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES) #if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)
dev = dev_find_slot(bus, devfn); dev = dev_find_slot(bus, devfn);
DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n", DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n",
__func__, dev_path(dev)); __func__, dev_path(dev));
if (dev == 0) { if (dev == 0) {
// fail accesses to non-existent devices... // fail accesses to non-existent devices...
#else #else
dev = bios_device.dev; dev = bios_device.dev;
if ((bus != bios_device.bus) if ((bus != bios_device.bus)
|| (devfn != bios_device.devfn)) { || (devfn != bios_device.devfn)) {
// fail accesses to any device but ours... // fail accesses to any device but ours...
#endif #endif
printf printf
("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n", ("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n",
__func__, bus, bios_device.bus, devfn, __func__, bus, bios_device.bus, devfn,
bios_device.devfn, offs); bios_device.devfn, offs);
SET_FLAG(F_CF); SET_FLAG(F_CF);
HALT_SYS(); HALT_SYS();
return 0; return 0;
} else { } else {
#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) #if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
switch (size) { switch (size) {
case 1: case 1:
rval = pci_read_config8(dev, offs); rval = pci_read_config8(dev, offs);
break; break;
case 2: case 2:
rval = pci_read_config16(dev, offs); rval = pci_read_config16(dev, offs);
break; break;
case 4: case 4:
rval = pci_read_config32(dev, offs); rval = pci_read_config32(dev, offs);
break; break;
}
#else
rval =
(u32) rtas_pci_config_read(bios_device.
puid, size,
bus, devfn,
offs);
#endif
DEBUG_PRINTF_IO
("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
__func__, addr, offs, size, rval);
}
} }
#else
rval =
(u32) rtas_pci_config_read(bios_device.
puid, size,
bus, devfn,
offs);
#endif
DEBUG_PRINTF_IO
("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
__func__, addr, offs, size, rval);
} }
return rval; return rval;
} }
@ -477,50 +480,54 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
void void
pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size) pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
{ {
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) { u32 port_cf8_val = 0;
// PCI Configuration Mechanism 1 step 1 u8 bus, devfn, offs;
// write to 0xCF8, sets bus, device, function and Config Space offset
// later write to 0xCFC-0xCFF sets the value... // PCI Configuration Mechanism 1 step 1
u8 bus, devfn, offs; // write to 0xCF8, sets bus, device, function and Config Space offset
u32 port_cf8_val = my_inl(0xCF8); // later write to 0xCFC-0xCFF sets the value...
if ((port_cf8_val & 0x80000000) != 0) {
//highest bit enables config space mapping if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
bus = (port_cf8_val & 0x00FF0000) >> 16; port_cf8_val = my_inl(0xCF8);
devfn = (port_cf8_val & 0x0000FF00) >> 8;
offs = (port_cf8_val & 0x000000FF); if ((port_cf8_val & 0x80000000) == 0)
offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly return;
if ((bus != bios_device.bus)
|| (devfn != bios_device.devfn)) { //highest bit enables config space mapping
// fail accesses to any device but ours... bus = (port_cf8_val & 0x00FF0000) >> 16;
printf devfn = (port_cf8_val & 0x0000FF00) >> 8;
("Config write access invalid! PCI device %x:%x.%x, offs: %x\n", offs = (port_cf8_val & 0x000000FF);
bus, devfn >> 3, devfn & 7, offs); offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
if ((bus != bios_device.bus)
|| (devfn != bios_device.devfn)) {
// fail accesses to any device but ours...
printf
("Config write access invalid! PCI device %x:%x.%x, offs: %x\n",
bus, devfn >> 3, devfn & 7, offs);
#if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG) #if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG)
HALT_SYS(); HALT_SYS();
#endif #endif
} else { } else {
#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) #if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
switch (size) { switch (size) {
case 1: case 1:
pci_write_config8(bios_device.dev, offs, val); pci_write_config8(bios_device.dev, offs, val);
break; break;
case 2: case 2:
pci_write_config16(bios_device.dev, offs, val); pci_write_config16(bios_device.dev, offs, val);
break; break;
case 4: case 4:
pci_write_config32(bios_device.dev, offs, val); pci_write_config32(bios_device.dev, offs, val);
break; break;
}
#else
rtas_pci_config_write(bios_device.puid,
size, bus, devfn, offs,
val);
#endif
DEBUG_PRINTF_IO
("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
__func__, addr, offs, size, val);
}
} }
#else
rtas_pci_config_write(bios_device.puid,
size, bus, devfn, offs,
val);
#endif
DEBUG_PRINTF_IO
("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
__func__, addr, offs, size, val);
} }
} }