GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

device/oprom: Reduce indentation 

Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-07-04 06:12:55 +03:00
parent b28b6b53cc
commit 8261d67ae7
1 changed files with 101 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
src/device/oprom/yabel/io.c
View File

@ -410,15 +410,20 @@ my_outl(X86EMU_pioAddr addr, u32 val)
u32
pci_cfg_read(X86EMU_pioAddr addr, u8 size)
{
u32 port_cf8_val = 0;
u32 rval = 0xFFFFFFFF;
struct device * dev;
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
struct device *dev = NULL;
u8 bus, devfn, offs;
// PCI Configuration Mechanism 1 step 1
// write to 0xCF8, sets bus, device, function and Config Space offset
// later read from 0xCFC-0xCFF returns the value...
u8 bus, devfn, offs;
u32 port_cf8_val = my_inl(0xCF8);
if ((port_cf8_val & 0x80000000) != 0) {
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
port_cf8_val = my_inl(0xCF8);
if ((port_cf8_val & 0x80000000) == 0)
return rval;
//highest bit enables config space mapping
bus = (port_cf8_val & 0x00FF0000) >> 16;
devfn = (port_cf8_val & 0x0000FF00) >> 8;
@ -469,21 +474,25 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
__func__, addr, offs, size, rval);
}
}
}
return rval;
}
void
pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
{
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
u32 port_cf8_val = 0;
u8 bus, devfn, offs;
// PCI Configuration Mechanism 1 step 1
// write to 0xCF8, sets bus, device, function and Config Space offset
// later write to 0xCFC-0xCFF sets the value...
u8 bus, devfn, offs;
u32 port_cf8_val = my_inl(0xCF8);
if ((port_cf8_val & 0x80000000) != 0) {
if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
port_cf8_val = my_inl(0xCF8);
if ((port_cf8_val & 0x80000000) == 0)
return;
//highest bit enables config space mapping
bus = (port_cf8_val & 0x00FF0000) >> 16;
devfn = (port_cf8_val & 0x0000FF00) >> 8;
@ -521,8 +530,6 @@ pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
__func__, addr, offs, size, val);
}
}
}
}
u8
handle_port_61h(void)