device/oprom: Reduce indentation
Change-Id: Iadae9221f7ea549e91cdc501155de058c51a982c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
This commit is contained in:
Kyösti Mälkki
parent
b28b6b53cc
commit
8261d67ae7
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@ -410,66 +410,69 @@ my_outl(X86EMU_pioAddr addr, u32 val)
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u32
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pci_cfg_read(X86EMU_pioAddr addr, u8 size)
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{
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u32 port_cf8_val = 0;
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u32 rval = 0xFFFFFFFF;
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struct device * dev;
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later read from 0xCFC-0xCFF returns the value...
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u8 bus, devfn, offs;
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u32 port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
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__func__, bus, devfn, offs);
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struct device *dev = NULL;
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u8 bus, devfn, offs;
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later read from 0xCFC-0xCFF returns the value...
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
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port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) == 0)
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return rval;
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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DEBUG_PRINTF_INTR("%s(): PCI Config Read from device: bus: %02x, devfn: %02x, offset: %02x\n",
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__func__, bus, devfn, offs);
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#if CONFIG(YABEL_PCI_ACCESS_OTHER_DEVICES)
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dev = dev_find_slot(bus, devfn);
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DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n",
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__func__, dev_path(dev));
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if (dev == 0) {
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// fail accesses to non-existent devices...
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dev = dev_find_slot(bus, devfn);
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DEBUG_PRINTF_INTR("%s(): dev_find_slot() returned: %s\n",
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__func__, dev_path(dev));
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if (dev == 0) {
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// fail accesses to non-existent devices...
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#else
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dev = bios_device.dev;
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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dev = bios_device.dev;
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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#endif
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printf
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("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n",
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__func__, bus, bios_device.bus, devfn,
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bios_device.devfn, offs);
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SET_FLAG(F_CF);
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HALT_SYS();
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return 0;
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} else {
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printf
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("%s(): Config read access invalid device! bus: %02x (%02x), devfn: %02x (%02x), offs: %02x\n",
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__func__, bus, bios_device.bus, devfn,
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bios_device.devfn, offs);
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SET_FLAG(F_CF);
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HALT_SYS();
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return 0;
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} else {
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#if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
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switch (size) {
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case 1:
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rval = pci_read_config8(dev, offs);
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break;
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case 2:
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rval = pci_read_config16(dev, offs);
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break;
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case 4:
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rval = pci_read_config32(dev, offs);
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break;
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}
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#else
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rval =
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(u32) rtas_pci_config_read(bios_device.
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puid, size,
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bus, devfn,
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offs);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
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__func__, addr, offs, size, rval);
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}
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switch (size) {
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case 1:
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rval = pci_read_config8(dev, offs);
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break;
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case 2:
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rval = pci_read_config16(dev, offs);
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break;
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case 4:
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rval = pci_read_config32(dev, offs);
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break;
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}
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#else
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rval =
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(u32) rtas_pci_config_read(bios_device.
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puid, size,
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bus, devfn,
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offs);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
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__func__, addr, offs, size, rval);
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}
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return rval;
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}
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@ -477,50 +480,54 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
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void
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pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
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{
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later write to 0xCFC-0xCFF sets the value...
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u8 bus, devfn, offs;
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u32 port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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printf
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("Config write access invalid! PCI device %x:%x.%x, offs: %x\n",
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bus, devfn >> 3, devfn & 7, offs);
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u32 port_cf8_val = 0;
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u8 bus, devfn, offs;
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later write to 0xCFC-0xCFF sets the value...
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if ((addr >= 0xCFC) && ((addr + size) <= 0xD00))
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port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) == 0)
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return;
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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printf
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("Config write access invalid! PCI device %x:%x.%x, offs: %x\n",
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bus, devfn >> 3, devfn & 7, offs);
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#if !CONFIG(YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG)
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HALT_SYS();
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HALT_SYS();
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#endif
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} else {
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} else {
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#if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
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switch (size) {
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case 1:
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pci_write_config8(bios_device.dev, offs, val);
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break;
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case 2:
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pci_write_config16(bios_device.dev, offs, val);
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break;
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case 4:
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pci_write_config32(bios_device.dev, offs, val);
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break;
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}
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#else
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rtas_pci_config_write(bios_device.puid,
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size, bus, devfn, offs,
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val);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
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__func__, addr, offs, size, val);
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}
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switch (size) {
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case 1:
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pci_write_config8(bios_device.dev, offs, val);
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break;
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case 2:
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pci_write_config16(bios_device.dev, offs, val);
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break;
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case 4:
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pci_write_config32(bios_device.dev, offs, val);
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break;
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}
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#else
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rtas_pci_config_write(bios_device.puid,
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size, bus, devfn, offs,
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val);
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#endif
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
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__func__, addr, offs, size, val);
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}
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}
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