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mb/clevo/l140cu: Remove unnecessary device declarations 

Remove unnecessary device declarations and remove comments where SMBIOS
slot descriptions are used.

Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-12-06 04:58:23 +01:00 committed by Michael Niewöhner
parent e9da62a05f
commit 8271cce959
1 changed files with 1 additions and 3 deletions
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4
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
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@ -141,7 +141,7 @@ chip soc/intel/cannonlake
device pci 1c.6 off end # PCI Express Port 7 device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8 device pci 1c.7 on # PCI Express Port 8
chip drivers/wifi/generic chip drivers/wifi/generic
device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) device pci 00.0 on end
end end
register "PcieRpEnable[7]" = "1" register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1"
@ -151,7 +151,6 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end end
device pci 1d.0 on # PCI Express Port 9 device pci 1d.0 on # PCI Express Port 9
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcUsage[4]" = "8"
@ -163,7 +162,6 @@ chip soc/intel/cannonlake
device pci 1d.2 off end # PCI Express Port 11 device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13 device pci 1d.4 on # PCI Express Port 13
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "1" register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12" register "PcieClkSrcUsage[5]" = "12"