soc/intel/icelake: Fix AG3E programming in PMC
According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped register but not pci configuration spaces, hence change the programming method in icelake pmc driver. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7 Reviewed-on: https://review.coreboot.org/c/30947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -31,8 +31,9 @@
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static void pmc_set_afterg3(struct device *dev, int s5pwr)
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{
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uint8_t reg8;
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uint8_t *pmcbase = pmc_mmio_regs();
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reg8 = pci_read_config8(dev, GEN_PMCON_B);
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reg8 = read8(pmcbase + GEN_PMCON_A);
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switch (s5pwr) {
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case MAINBOARD_POWER_STATE_OFF:
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@ -46,7 +47,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr)
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break;
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}
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pci_write_config8(dev, GEN_PMCON_B, reg8);
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write8(pmcbase + GEN_PMCON_A, reg8);
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}
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/*
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