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soc/intel/icelake: Fix AG3E programming in PMC 

According to EDS #571034 4.3.2, GEN_PMCON_A stays in pmc mmio mapped
register but not pci configuration spaces, hence change the programming
method in icelake pmc driver.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I29883b50cdca99b45f5362f78cbee32beaa669f7
Reviewed-on: https://review.coreboot.org/c/30947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Lijian Zhao 2019-01-15 19:06:09 -08:00 committed by Patrick Georgi
parent d1215269a7
commit 82b8c3d1b0
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/icelake/pmc.c
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@ -31,8 +31,9 @@
static void pmc_set_afterg3(struct device *dev, int s5pwr) static void pmc_set_afterg3(struct device *dev, int s5pwr)
{ {
uint8_t reg8; uint8_t reg8;
uint8_t *pmcbase = pmc_mmio_regs();
reg8 = pci_read_config8(dev, GEN_PMCON_B); reg8 = read8(pmcbase + GEN_PMCON_A);
switch (s5pwr) { switch (s5pwr) {
case MAINBOARD_POWER_STATE_OFF: case MAINBOARD_POWER_STATE_OFF:
@ -46,7 +47,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr)
break; break;
} }
pci_write_config8(dev, GEN_PMCON_B, reg8); write8(pmcbase + GEN_PMCON_A, reg8);
} }
/* /*