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intel/tigerlake: Add Acoustic features 

On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.

BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Shaunak Saha 2021-02-17 23:26:43 -08:00 committed by Furquan Shaikh
parent 967753f0d8
commit 82d5123e1c
8 changed files with 15 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -352,6 +352,11 @@ chip soc/intel/tigerlake
.vnn_sx_voltage_mv = 1250,
}"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate" = "SLEW_FAST_8"
register "FastPkgCRampDisable" = "1"
device domain 0 on
device ref igpu on end
device ref dptf on

11
src/mainboard/google/volteer/variants/delbin/overridetree.cb
View File

@ -57,17 +57,6 @@ chip soc/intel/tigerlake
}"
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
register "tcc_offset" = "8"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{

11
src/mainboard/google/volteer/variants/drobit/overridetree.cb
View File

@ -2,17 +2,6 @@ chip soc/intel/tigerlake
register "DdiPort1Hpd" = "0"
register "DdiPort2Hpd" = "0"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
register "tcc_offset" = "8"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{

11
src/mainboard/google/volteer/variants/volteer/overridetree.cb
View File

@ -49,17 +49,6 @@ chip soc/intel/tigerlake
register "HybridStorageMode" = "1"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
device domain 0 on
device ref ipu on end
device ref i2c0 on

11
src/mainboard/google/volteer/variants/volteer2/overridetree.cb
View File

@ -65,17 +65,6 @@ chip soc/intel/tigerlake
register "HybridStorageMode" = "1"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
device domain 0 on
device ref dptf on
chip drivers/intel/dptf

11
src/mainboard/google/volteer/variants/voxel/overridetree.cb
View File

@ -19,17 +19,6 @@ chip soc/intel/tigerlake
# Disable SRCCLKREQ1#
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
# Acoustic settings
register "AcousticNoiseMitigation" = "1"
register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_SA]" = "SLEW_FAST_8"
register "SlowSlewRate[VR_DOMAIN_VLCC]" = "SLEW_FAST_8"
register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1"
register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1"
device domain 0 on
device ref dptf on
chip drivers/intel/dptf

17
src/soc/intel/tigerlake/chip.h
View File

@ -186,22 +186,21 @@ struct soc_intel_tigerlake_config {
/*
* Offset 0x054B - Disable Fast Slew Rate for Deep Package
* C States for VR domains. Disable Fast Slew Rate for Deep
* Package C States based on Acoustic Noise Mitigation feature
* enabled. The domains are IA,GT,SA,VLCC and FIVR.
* C States for VCCin in VR domain. Disable Fast Slew Rate
* for Deep Package C States based on Acoustic Noise
* Mitigation feature enabled.
* 0 - False
* 1 - True
*/
uint8_t FastPkgCRampDisable[VR_DOMAIN_MAX];
uint8_t FastPkgCRampDisable;
/*
* Offset 0x0550 - Slew Rate configuration for Deep Package
* C States for VR domains. Slew Rate configuration for Deep
* Package C States for VR domains based on Acoustic Noise
* Mitigation feature enabled. The domains are IA,GT,SA,VLCC and FIVR.
* Slew rates are defined as enum slew_rate.
* C States for VCCin in VR domain. Slew Rate configuration
* for Deep Package C States for VR domain based on Acoustic
* Noise Mitigation feature enabled.
*/
uint8_t SlowSlewRate[VR_DOMAIN_MAX];
uint8_t SlowSlewRate;
/* SATA related */
uint8_t SataEnable;

8
src/soc/intel/tigerlake/fsp_params.c
View File

@ -332,12 +332,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
params->AcousticNoiseMitigation = config->AcousticNoiseMitigation;
memcpy(&params->SlowSlewRate, &config->SlowSlewRate,
ARRAY_SIZE(config->SlowSlewRate) * sizeof(config->SlowSlewRate[0]));
memcpy(&params->FastPkgCRampDisable, &config->FastPkgCRampDisable,
ARRAY_SIZE(config->FastPkgCRampDisable) *
sizeof(config->FastPkgCRampDisable[0]));
params->FastPkgCRampDisable[0] = config->FastPkgCRampDisable;
params->SlowSlewRate[0] = config->SlowSlewRate;
/* Enable TCPU for processor thermal control */
params->Device4Enable = config->Device4Enable;