mb/x/acpi_tables: Move EC_RW detection
These boards without ChromeEC do not set ACTIVE_EC_RW flag as part of the gnvs_assign_chromeos() function. Create abstraction to avoid <vendorcode/chromeos/x> include. Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,3 +18,12 @@ void gnvs_assign_chromeos(void)
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if (CONFIG(EC_GOOGLE_CHROMEEC) && !google_ec_running_ro())
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gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
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}
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void gnvs_set_ecfw_rw(void)
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{
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chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
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if (!gnvs_chromeos)
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return;
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gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
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}
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@ -10,6 +10,7 @@ void *gnvs_get_or_create(void);
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void acpi_inject_nvsa(void);
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void gnvs_assign_chromeos(void);
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void gnvs_set_ecfw_rw(void);
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/* Platform code must implement these. */
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struct global_nvs;
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@ -3,10 +3,8 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <ec/google/chromeec/ec.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <variant/thermal.h>
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void acpi_create_gnvs(struct global_nvs *gnvs)
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@ -22,11 +20,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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/* TPM Present */
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gnvs->tpmp = 1;
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#if CONFIG(CHROMEOS)
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// SuperIO is always RO
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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#endif
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gnvs->f4of = FAN4_THRESHOLD_OFF;
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gnvs->f4on = FAN4_THRESHOLD_ON;
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gnvs->f4pw = FAN4_PWM;
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@ -2,7 +2,6 @@
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#include <acpi/acpi_gnvs.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include "thermal.h"
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void acpi_create_gnvs(struct global_nvs *gnvs)
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@ -19,7 +18,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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// The firmware read/write status is a "virtual" switch and
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// will be handled elsewhere. Until then hard-code to
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// read/write instead of read-only for developer mode.
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
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if (CONFIG(CHROMEOS))
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gnvs_set_ecfw_rw();
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// the lid is open by default.
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gnvs->lids = 1;
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@ -27,5 +27,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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/* EC handles all thermal and fan control on Butterfly. */
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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@ -3,7 +3,6 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <ec/compal/ene932/ec.h>
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#include "ec.h"
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@ -22,10 +21,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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#if CONFIG(CHROMEOS)
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gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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#endif
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if (CONFIG(CHROMEOS) && !parrot_ec_running_ro())
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gnvs_set_ecfw_rw();
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/* EC handles all active thermal and fan control on Parrot. */
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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@ -3,7 +3,6 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <bootmode.h>
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#include <ec/quanta/it8518/ec.h>
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#include "ec.h"
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@ -23,10 +22,8 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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#if CONFIG(CHROMEOS)
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gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
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ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
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#endif
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if (CONFIG(CHROMEOS) && !get_recovery_mode_switch())
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gnvs_set_ecfw_rw();
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/* EC handles all thermal and fan control on Stout. */
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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@ -3,7 +3,6 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <southbridge/intel/lynxpoint/pch.h>
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#include <southbridge/intel/lynxpoint/nvs.h>
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@ -25,11 +24,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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/* TPM Present */
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gnvs->tpmp = 1;
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#if CONFIG(CHROMEOS)
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/* Emerald Lake has no EC (?) */
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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#endif
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gnvs->f4of = FAN4_THRESHOLD_OFF;
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gnvs->f4on = FAN4_THRESHOLD_ON;
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gnvs->f4pw = FAN4_PWM;
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@ -3,7 +3,6 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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@ -44,7 +43,4 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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// Stumpy has no arms^H^H^H^HEC.
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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}
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@ -4,9 +4,6 @@
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <ec/acpi/ec.h>
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#if CONFIG(CHROMEOS)
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#include <vendorcode/google/chromeos/gnvs.h>
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#endif
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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@ -47,5 +44,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
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gnvs->tmax = MAX_TEMPERATURE;
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gnvs->flvl = 5;
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gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO;
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if (CONFIG(CHROMEOS) && ec_read(0xcb))
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gnvs_set_ecfw_rw();
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}
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@ -3,7 +3,6 @@
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#include <acpi/acpi.h>
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#include <acpi/acpi_gnvs.h>
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#include <device/device.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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gnvs->tmax = MAX_TEMPERATURE;
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gnvs->flvl = 5;
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// Stumpy has no arms^H^H^H^HEC.
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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}
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