Change all vx800 file names from CamelCase to camel_case to match
our coding guidelines (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -197,59 +197,59 @@ typedef struct _DRAM_SIZE_INFO {
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//detection.c
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/*Step1 detect DRAM type, Read SPD data,command rate*/
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CB_STATUS DRAMDetect(DRAM_SYS_ATTR * DramAttr);
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//FreqSetting.c
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//freq_setting.c
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/*Step2 set Frequency, calculate CAL*/
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void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr);
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//TimingSetting.c
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//timing_setting.c
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/*Step3 Set DRAM Timing*/
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void DRAMTimingSetting(DRAM_SYS_ATTR * DramAttr);
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//DRDY_BL.c
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//drdy_bl.c
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/*Step4 DRDY*/
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void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr);
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//DRDY_BL.c
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//drdy_bl.c
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/*Step5 Burst Length*/
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void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr);
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//DrivingSetting.c
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//driving_setting.c
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/*Step6 DRAM Driving Adjustment*/
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void DRAMDriving(DRAM_SYS_ATTR * DramAttr);
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//ClkCtrl.c
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//clk_ctrl.c
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/*Step7 duty cycle control*/
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void DutyCycleCtrl(DRAM_SYS_ATTR * DramAttr);
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//ClkCtrl.c
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//clk_ctrl.c
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/*Step8 DRAM clock phase and delay control*/
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void DRAMClkCtrl(DRAM_SYS_ATTR * DramAttr);
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//DevInit.c
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//dev_init.c
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/*Step9 set register before init DRAM device*/
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void DRAMRegInitValue(DRAM_SYS_ATTR * DramAttr);
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//DevInit.c
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//dev_init.c
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/*Step10 DDR and DDR2 initialize process*/
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void DRAMInitializeProc(DRAM_SYS_ATTR * DramAttr);
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//DQSSearch.c
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//dqs_search.c
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/*Step11 Search DQS and DQ output delay*/
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void DRAMDQSOutputSearch(DRAM_SYS_ATTR * DramAttr);
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//DQSSearch.c
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//dqs_search.c
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/*Step12 Search DQS input delay*/
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void DRAMDQSInputSearch(DRAM_SYS_ATTR * DramAttr);
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//RankMap.c
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//rank_map.c
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/*Step13 Interleav function in rankmap.c*/
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void DRAMBankInterleave(DRAM_SYS_ATTR * DramAttr);
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//RankMap.c
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//rank_map.c
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/*Step14 Sizing*/
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void DRAMSizingMATypeM(DRAM_SYS_ATTR * DramAttr);
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//FinalSetting.c
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//final_setting.c
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/*Step15 DDR fresh counter setting*/
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void DRAMRefreshCounter(DRAM_SYS_ATTR * DramAttr);
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//FinnalSetting.c
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//final_setting.c
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/*Step16 Final register setting for improve performance*/
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void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr);
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@ -396,7 +396,7 @@ void InitDDR2CHA(DRAM_SYS_ATTR * DramAttr)
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// Step 9,10. check ODT value for EMRS(1) command
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// according to ODTLookUp_TBL in DrivingSetting.c if there is one dimm in MB's one channel , the DDR2's ODT is 150ohm
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// according to ODTLookUp_TBL in driving_setting.c if there is one dimm in MB's one channel , the DDR2's ODT is 150ohm
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// if there is two dimm in MB's one channel, the DDR2's ODT is 75 ohm
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DimmNum = DramAttr->DimmNumChA;
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@ -43,7 +43,7 @@
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "DrivingClkPhaseData.c"
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#include "driving_clk_phase_data.c"
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#include "northbridge/via/vx800/raminit.h"
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#include "northbridge/via/vx800/raminit.c"
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@ -423,7 +423,7 @@ g) Rx73h = 32h
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DRAMDRDYSetting(&DramAttr);
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Data = 0x80; // this value is same with DevInit.c
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Data = 0x80; // this value is same with dev_init.c
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pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data);
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pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2);
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Data = pci_read_config8(MEMCTRL, 0x88);
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@ -18,7 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "northbridge/via/vx800/DrivingClkPhaseData.h"
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#include "northbridge/via/vx800/driving_clk_phase_data.h"
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// DQS Driving
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//Reg0xE0, 0xE1
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@ -38,7 +38,7 @@
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static void memctrl_init(device_t dev)
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{
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/*
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set VGA in UMARamSetting.c, not in this function.
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set VGA in uma_ram_setting.c, not in this function.
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*/
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#if 0
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pci_write_config8(dev, 0x85, 0x20);
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@ -38,24 +38,24 @@
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#define PRINT_DEBUG_MEM_HEX32(x)
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#define DUMPNORTH()
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#endif
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#include "northbridge/via/vx800/ddr2init/Translatorddr2init.c"
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#include "northbridge/via/vx800/ddr2init/DramInit.h"
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#include "northbridge/via/vx800/ddr2init/translator_ddr2_init.c"
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#include "northbridge/via/vx800/ddr2init/dram_init.h"
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#include "northbridge/via/vx800/vx800_early_smbus.c"
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#include "northbridge/via/vx800/vx800_early_serial.c"
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#include "northbridge/via/vx800/ddr2init/DramUtil.h"
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#include "northbridge/via/vx800/ddr2init/DramUtil.c"
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#include "northbridge/via/vx800/ddr2init/vx800/Detection.c"
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#include "northbridge/via/vx800/ddr2init/vx800/FreqSetting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/TimingSetting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/DRDY_BL.c"
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#include "northbridge/via/vx800/ddr2init/vx800/DrivingSetting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/ClkCtrl.c"
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#include "northbridge/via/vx800/ddr2init/vx800/DevInit.c"
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#include "northbridge/via/vx800/ddr2init/vx800/RankMap.c"
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#include "northbridge/via/vx800/ddr2init/vx800/DQSSearch.c"
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#include "northbridge/via/vx800/ddr2init/vx800/FinalSetting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/UMARamSetting.c"
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#include "northbridge/via/vx800/ddr2init/DramInit.c"
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#include "northbridge/via/vx800/ddr2init/dram_util.h"
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#include "northbridge/via/vx800/ddr2init/dram_util.c"
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#include "northbridge/via/vx800/ddr2init/vx800/detection.c"
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#include "northbridge/via/vx800/ddr2init/vx800/freq_setting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/timing_setting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/drdy_bl.c"
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#include "northbridge/via/vx800/ddr2init/vx800/driving_setting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/clk_ctrl.c"
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#include "northbridge/via/vx800/ddr2init/vx800/dev_init.c"
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#include "northbridge/via/vx800/ddr2init/vx800/rank_map.c"
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#include "northbridge/via/vx800/ddr2init/vx800/dqs_search.c"
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#include "northbridge/via/vx800/ddr2init/vx800/final_setting.c"
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#include "northbridge/via/vx800/ddr2init/vx800/uma_ram_setting.c"
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#include "northbridge/via/vx800/ddr2init/dram_init.c"
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/*
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* Support one dimm with up to 2 ranks
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*/
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