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intel/model_2065x: Prepare for dynamic CONFIG_RAMTOP 

Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15230
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-17 10:00:28 +03:00
parent b4f827d45a
commit 8431fcb8c8
4 changed files with 13 additions and 7 deletions
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1
src/cpu/intel/model_2065x/Makefile.inc
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@ -20,3 +20,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc cpu_incs-y += $(src)/cpu/intel/model_2065x/cache_as_ram.inc
romstage-y += ../car/romstage.c

10
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@ -170,7 +170,12 @@ clear_var_mtrrs:
before_romstage: before_romstage:
post_code(0x29) post_code(0x29)
/* Call romstage.c main function. */ /* Call romstage.c main function. */
call main call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x2f) post_code(0x2f)
@ -272,7 +277,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE) post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */ cld /* Clear direction flag. */
movl $CONFIG_RAMTOP, %esp /* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
movl %esp, %ebp movl %esp, %ebp
call copy_and_run call copy_and_run

4
src/mainboard/lenovo/x201/romstage.c
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@ -28,6 +28,7 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <delay.h> #include <delay.h>
#include <timestamp.h> #include <timestamp.h>
@ -174,8 +175,7 @@ static void set_fsb_frequency(void)
smbus_block_write(0x69, 0, 5, block); smbus_block_write(0x69, 0, 5, block);
} }
#include <cpu/intel/romstage.h> void mainboard_romstage_entry(unsigned long bist)
void main(unsigned long bist)
{ {
u32 reg32; u32 reg32;
int s3resume = 0; int s3resume = 0;

5
src/mainboard/packardbell/ms2290/romstage.c
View File

@ -28,12 +28,12 @@
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
#include <ec/acpi/ec.h> #include <ec/acpi/ec.h>
#include <delay.h> #include <delay.h>
#include <timestamp.h> #include <timestamp.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <cpu/intel/romstage.h>
#include "arch/early_variables.h" #include "arch/early_variables.h"
#include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/pch.h>
@ -166,8 +166,7 @@ static inline u16 read_acpi16(u32 addr)
} }
#endif #endif
#include <cpu/intel/romstage.h> void mainboard_romstage_entry(unsigned long bist)
void main(unsigned long bist)
{ {
u32 reg32; u32 reg32;
int s3resume = 0; int s3resume = 0;