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soc/intel/tigerlake: Drop unused SataEnable setting 

`SataEnable` is set by some boards, but it doesn't have any effect since
its related FSP option is hooked up to the devicetree state. Thus, drop
it.

Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Felix Singer 2021-12-05 02:45:51 +01:00
parent 83d54c30fa
commit 8474f4dc9b
3 changed files with 0 additions and 3 deletions
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1
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
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@ -25,7 +25,6 @@ chip soc/intel/tigerlake
# FSP configuration # FSP configuration
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Disabled"
register "SataEnable" = "1"
register "SataMode" = "0" register "SataMode" = "0"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"

1
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -146,7 +146,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA # Enable SATA
register "SataEnable" = "1"
register "SataMode" = "0" register "SataMode" = "0"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "0" register "SataPortsEnable[0]" = "0"

1
src/soc/intel/tigerlake/chip.h
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@ -215,7 +215,6 @@ struct soc_intel_tigerlake_config {
uint8_t SlowSlewRate; uint8_t SlowSlewRate;
/* SATA related */ /* SATA related */
uint8_t SataEnable;
uint8_t SataMode; uint8_t SataMode;
uint8_t SataSalpSupport; uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8]; uint8_t SataPortsEnable[8];