soc/intel/tigerlake: Enable CNVi Mode

Add configs to enable CNVi mode and CNViBtCore.

BUG=none
BRANCH=none
TEST=Build and boot tglrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/chip.h

@@ -208,6 +208,10 @@ struct soc_intel_tigerlake_config {
 	/* Enable Pch iSCLK */
 	uint8_t pch_isclk;
 
+	/* CNVi */
+	uint8_t CnviMode;
+	uint8_t CnviBtCore;
+
 	/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
 	enum {
 		FORCE_DISABLE,

src/soc/intel/tigerlake/fsp_params_tgl.c

@@ -149,6 +149,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	else
 		params->PchLanEnable = dev->enabled;
 
+	/* CNVi */
+	params->CnviMode = config->CnviMode;
+	params->CnviBtCore = config->CnviBtCore;
+
 	/* Legacy 8254 timer support */
 	params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
 	params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;