Documentation/mainboard: Add emulation/spike-riscv.md
Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
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# Spike RISC-V emulator
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[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.
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## Installation
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- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/>
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- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,
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which are necessary in order to have a serial console
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- Compile `riscv-fesvr` and then `riscv-isa-sim`
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## Building coreboot and running it in Spike
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- Configure coreboot and run `make` as usual
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- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
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convert coreboot to an ELF that Spike can load
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- Run `spike -m1024 build/coreboot.elf`
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[Spike]: https://github.com/riscv/riscv-isa-sim
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[RISC-V]: https://riscv.org/
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@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards.
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- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
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## Emulation
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The boards in this section are not real mainboards, but emulators.
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- [Spike RISC-V emulator](emulation/spike-riscv.md)
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## Foxconn
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- [D41S](foxconn/d41s.md)
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@ -1,7 +1,3 @@
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config BOARD_EMULATION_SPIKE_RISCV
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bool "SPIKE riscv"
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help
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To run coreboot in spike:
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* run "make" as usual
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* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
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* spike -m1024 build/coreboot.elf
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