Documentation/mainboard: Add emulation/spike-riscv.md

Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.

Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
This commit is contained in:
Jonathan Neuschäfer 2018-10-28 02:48:25 +02:00 committed by Philipp Deppenwiese
parent c5f4a8c8f0
commit 84bf089f6a
3 changed files with 29 additions and 4 deletions

View File

@ -0,0 +1,23 @@
# Spike RISC-V emulator
[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.
## Installation
- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/>
- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,
which are necessary in order to have a serial console
- Compile `riscv-fesvr` and then `riscv-isa-sim`
## Building coreboot and running it in Spike
- Configure coreboot and run `make` as usual
- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
convert coreboot to an ELF that Spike can load
- Run `spike -m1024 build/coreboot.elf`
[Spike]: https://github.com/riscv/riscv-isa-sim
[RISC-V]: https://riscv.org/

View File

@ -10,6 +10,12 @@ This section contains documentation about coreboot on specific mainboards.
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
## Emulation
The boards in this section are not real mainboards, but emulators.
- [Spike RISC-V emulator](emulation/spike-riscv.md)
## Foxconn
- [D41S](foxconn/d41s.md)

View File

@ -1,7 +1,3 @@
config BOARD_EMULATION_SPIKE_RISCV
bool "SPIKE riscv"
help
To run coreboot in spike:
* run "make" as usual
* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
* spike -m1024 build/coreboot.elf