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OxPCIe952: Fix read8/write8 argument 

This was missed in commit bde6d309 as the driver is not enabled
in any configuration by default.

Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8660
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2015-03-12 11:33:14 +02:00
parent f9fb0d9bf3
commit 8517f94bfd
2 changed files with 5 additions and 4 deletions
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5
src/drivers/uart/oxpcie.c
View File

@ -34,11 +34,12 @@ static void oxford_oxpcie_enable(device_t dev)
printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
return; return;
} }
void *bar0 = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
(read32(res->base) >> 8), (read32(res->base) & 0xff)); (read32(bar0) >> 8), (read32(bar0) & 0xff));
printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
(read32(res->base + 4) & 3)); (read32(bar0 + 4) & 3));
printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
} }

4
src/drivers/uart/uart8250mem.c
View File

@ -36,12 +36,12 @@
static uint8_t uart8250_read(void *base, uint8_t reg) static uint8_t uart8250_read(void *base, uint8_t reg)
{ {
return read8((uintptr_t) (base + reg)); return read8(base + reg);
} }
static void uart8250_write(void *base, uint8_t reg, uint8_t data) static void uart8250_write(void *base, uint8_t reg, uint8_t data)
{ {
write8((uintptr_t) (base + reg), data); write8(base + reg, data);
} }
static int uart8250_mem_can_tx_byte(void *base) static int uart8250_mem_can_tx_byte(void *base)