OxPCIe952: Fix read8/write8 argument
This was missed in commit bde6d309
as the driver is not enabled
in any configuration by default.
Change-Id: I3d886531f5bcf013fc22ee0a1e8fa250d7c4c1a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8660
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
parent
f9fb0d9bf3
commit
8517f94bfd
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@ -34,11 +34,12 @@ static void oxford_oxpcie_enable(device_t dev)
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printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
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printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
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return;
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return;
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}
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}
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void *bar0 = res2mmio(res, 0, 0);
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printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
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printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n",
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(read32(res->base) >> 8), (read32(res->base) & 0xff));
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(read32(bar0) >> 8), (read32(bar0) & 0xff));
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printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
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printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
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(read32(res->base + 4) & 3));
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(read32(bar0 + 4) & 3));
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printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
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printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
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}
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}
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@ -36,12 +36,12 @@
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static uint8_t uart8250_read(void *base, uint8_t reg)
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static uint8_t uart8250_read(void *base, uint8_t reg)
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{
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{
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return read8((uintptr_t) (base + reg));
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return read8(base + reg);
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}
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}
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static void uart8250_write(void *base, uint8_t reg, uint8_t data)
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static void uart8250_write(void *base, uint8_t reg, uint8_t data)
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{
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{
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write8((uintptr_t) (base + reg), data);
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write8(base + reg, data);
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}
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}
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static int uart8250_mem_can_tx_byte(void *base)
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static int uart8250_mem_can_tx_byte(void *base)
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