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skylake: set DISB in GEN_PMCON_A register properly 

DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
training is complete. However, as a 8-bit write was
being performed the bit was never being set.

BUG=chrome-os-partner:43516
BRANCH=None
TEST=Built and booted to kernel. Rebooted. Noted full memory
     training was not being peformed.

Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290337
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11183
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2015-08-04 14:04:47 -05:00
parent c5b91d6800
commit 85654a6650
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/skylake/pmc.c
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@ -47,7 +47,7 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
/* Enable SCI and clear SLP requests. */ /* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN), REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
/* Indicate DRAM init done for MRC */ /* Indicate DRAM init done for MRC */
REG_PCI_OR8(GEN_PMCON_A, DISB), REG_PCI_OR32(GEN_PMCON_A, DISB),
REG_SCRIPT_END REG_SCRIPT_END
}; };