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soc/mediatek/mt8183: Improve DRAM calibration logs 

- Add macro dramc_err.
- Some log levels are changed.
- Some messages are improved for readability.

BRANCH=kukui
BUG=none
TEST=emerge-kukui coreboot

Change-Id: If0c9e61c0f81a06e9264784f682a6c373574e06b
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35767
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2019-10-03 09:45:16 +08:00 committed by Patrick Georgi
parent c5568a145f
commit 85ca1fe4e6
4 changed files with 19 additions and 24 deletions
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4
src/soc/mediatek/mt8183/dramc_pi_basic_api.c
View File

@ -128,8 +128,8 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
write32(&ch[0].ao.impcal, impcal_bak);
dramc_show("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n",
term, DRVP_result, DRVN_result, ODTN_result);
dramc_dbg("impedance: term=%d, DRVP=%d, DRVN=%d, ODTN=%d\n",
term, DRVP_result, DRVN_result, ODTN_result);
u32 *imp = impedance->data[term];
if (term == ODT_OFF) {
imp[0] = DRVP_result;

24
src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
View File

@ -1036,14 +1036,14 @@ static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank, u8 freq_group,
}
for (dqs = 0; dqs < DQS_NUMBER; dqs++)
dramc_show("Best DQS%d dly(2T, 0.5T, fine tune)"
" = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs],
best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);
dramc_dbg("Best DQS%d dly(2T, 0.5T, fine tune)"
" = (%d, %d, %d)\n", dqs, best_coarse_tune2t[dqs],
best_coarse_tune0p5t[dqs], best_fine_tune[dqs]);
for (dqs = 0; dqs < DQS_NUMBER; dqs++)
dramc_show("Best DQS%d P1 dly(2T, 0.5T, fine tune)"
" = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs],
best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]);
dramc_dbg("Best DQS%d P1 dly(2T, 0.5T, fine tune)"
" = (%d, %d, %d)\n", dqs, best_coarse_tune2t_p1[dqs],
best_coarse_tune0p5t_p1[dqs], best_fine_tune[dqs]);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
write32(regs_bak[i].addr, regs_bak[i].value);
@ -1189,7 +1189,7 @@ static void dramc_set_rx_dly_factor(u8 chn, u8 rank, enum RX_TYPE type, u32 val)
SHU1_R0_B0_DQ6_RK0_RX_ARDQS0_R_DLY_B0, val);
break;
default:
dramc_show("error calibration type:%d\n", type);
dramc_err("error calibration type: %d\n", type);
break;
}
}
@ -1302,7 +1302,7 @@ static void dramc_get_dly_range(u8 chn, u8 rank, enum CAL_TYPE type,
*end = *begin + 64;
break;
default:
dramc_show("error calibration type:%d\n", type);
dramc_err("error calibration type: %d\n", type);
break;
}
}
@ -1429,7 +1429,7 @@ static bool dramk_calc_best_vref(enum CAL_TYPE type, u8 vref,
break;
default:
dramc_show("error calibration type:%d\n", type);
dramc_err("error calibration type: %d\n", type);
break;
}
@ -1997,7 +1997,7 @@ static u8 dramc_rx_datlat_cal(u8 chn, u8 rank, u8 freq_group,
*test_passed = (sum != 0);
if (!*test_passed) {
dramc_show("DRAM memory test failed\n");
dramc_err("DRAM memory test failed\n");
return 0;
}
@ -2118,8 +2118,8 @@ int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group)
u8 rx_datlat[RANK_MAX] = {0};
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
for (u8 rk = RANK_0; rk < RANK_MAX; rk++) {
dramc_show("Start K: freq=%d, ch=%d, rank=%d\n",
freq_group, chn, rk);
dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n",
freq_group, chn, rk);
dramc_cmd_bus_training(chn, rk, freq_group, pams,
fast_calib);
dramc_write_leveling(chn, rk, freq_group, pams->wr_level);

14
src/soc/mediatek/mt8183/emi.c
View File

@ -434,7 +434,7 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
if (src_shuffle == dst_shuffle)
return;
dramc_show("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle);
dramc_dbg("Save shuffle %u to shuffle %u\n", src_shuffle, dst_shuffle);
for (chn = 0; chn < CHANNEL_MAX; chn++) {
/* DRAMC */
@ -449,7 +449,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
}
}
dramc_show("the dramc register of chn %d saved!\n", chn);
/* DRAMC-exception-1 */
src_addr = (u8 *)&ch[chn].ao.shuctrl2;
@ -461,8 +460,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16);
dramc_show("the dramc exception-1 register of chn %d saved!\n", chn);
/* DRAMC-exception-2 */
src_addr = (u8 *)&ch[chn].ao.dvfsdll;
value = (read32(src_addr) >> 1) & 0x1;
@ -472,8 +469,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
clrsetbits_le32(src_addr, 0x1 << 3, value << 3);
dramc_show("the dramc exception-2 register of chn %d saved!\n", chn);
/* PHY */
for (index = 0; index < ARRAY_SIZE(phy_regs); index++) {
for (offset = phy_regs[index].start;
@ -486,7 +481,6 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
}
}
dramc_show("the phy register of chn %d saved!\n", chn);
}
}
@ -507,7 +501,7 @@ static int run_calib(const struct dramc_param *dparam,
set_vcore_voltage(freq_group);
dramc_show("Run calibration (freq: %u, first: %d)\n",
freq_group, *first_run);
frequency_table[freq_group], *first_run);
if (*first_run)
init_dram(params, freq_group, impedance);
@ -515,11 +509,11 @@ static int run_calib(const struct dramc_param *dparam,
dfs_init_for_calibration(params, freq_group, impedance);
*first_run = false;
dramc_show("Start K (current clock: %u\n", params->frequency);
dramc_dbg("Start K (current clock: %u\n", params->frequency);
if (dramc_calibrate_all_channels(params, freq_group) != 0)
return -1;
dramc_ac_timing_optimize(freq_group);
dramc_show("K finished (current clock: %u\n", params->frequency);
dramc_dbg("K finished (current clock: %u\n", params->frequency);
dramc_save_result_to_shuffle(DRAM_DFS_SHUFFLE_1, shuffle);
return 0;

1
src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h
View File

@ -20,6 +20,7 @@
#include <soc/emi.h>
#include <console/console.h>
#define dramc_err(_x_...) printk(BIOS_ERR, _x_)
#define dramc_show(_x_...) printk(BIOS_INFO, _x_)
#if CONFIG(DEBUG_DRAM)
#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_)