- First pass at code for generic link width and size determination
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -473,7 +473,8 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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struct device *old_devices;
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struct device *child;
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#if HYPERTRANSPORT_SUPPORT
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unsigned next_unitid, last_unitid;
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unsigned next_unitid, last_unitid, previous_unitid;
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int reset_needed;
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#endif
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printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
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@ -486,20 +487,19 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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#if HYPERTRANSPORT_SUPPORT
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/* If present assign unitid to a hypertransport chain */
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next_unitid = 1;
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do {
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/* Spin through the devices and collapse any early
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* hypertransport enumeration.
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*/
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for(devfn = 0; devfn <= 0xff; devfn += 8) {
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struct device dummy;
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uint32_t id;
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uint8_t hdr_type, pos;
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last_unitid = next_unitid;
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dummy.bus = bus;
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dummy.devfn = 0;
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dummy.devfn = devfn;
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id = pci_read_config32(&dummy, PCI_VENDOR_ID);
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000) {
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break;
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continue;
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}
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hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
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pos = 0;
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@ -521,19 +521,151 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n", (unsigned)flags);
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if ((flags >> 13) == 0) {
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unsigned count;
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/* Clear the unitid */
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flags &= ~0x1f;
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flags |= next_unitid & 0x1f;
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count = (flags >> 5) & 0x1f;
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printk_debug("unitid: 0x%02x, count: 0x%02x\n",
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next_unitid, count);
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pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
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next_unitid += count;
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break;
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}
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}
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pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
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}
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}
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/* If present assign unitid to a hypertransport chain */
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last_unitid = 0;
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next_unitid = 1;
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do {
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struct device dummy;
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uint32_t id;
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uint8_t hdr_type, pos, previous_pos;
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previous_unitid = last_unitid;
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last_unitid = next_unitid;
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/* Read the next unassigned device off the stack */
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dummy.bus = bus;
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dummy.devfn = 0;
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id = pci_read_config32(&dummy, PCI_VENDOR_ID);
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/* If the chain is enumerated quit */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000) {
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break;
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}
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hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
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pos = 0;
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switch(hdr_type & 0x7f) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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pos = PCI_CAPABILITY_LIST;
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break;
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}
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if (pos > PCI_CAP_LIST_NEXT) {
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pos = pci_read_config8(&dummy, pos);
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}
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while(pos != 0) { /* loop through the linked list */
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uint8_t cap;
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cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
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printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
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if (cap == PCI_CAP_ID_HT) {
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uint16_t flags;
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uint16_t links;
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flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
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printk_debug("flags: 0x%04x\n", (unsigned)flags);
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if ((flags >> 13) == 0) { /* Entry is a Slave secondary */
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struct device last, previous;
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unsigned count;
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unsigned width;
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flags &= ~0x1f; /* mask out base unit ID */
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flags |= next_unitid & 0x1f; /* assign ID */
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count = (flags >> 5) & 0x1f; /* get unit count */
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printk_debug("unitid: 0x%02x, count: 0x%02x\n",
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next_unitid, count);
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pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
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next_unitid += count;
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if (previous_unitid == 0) { /* the link is back to the host */
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/* calculate the previous pos for the host */
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previous_pos = 0x80;
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previous.bus = 0;
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previous.devfn = 0x18 << 3;
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#warning "FIXME we should not hard code this!"
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} else {
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previous.bus = bus;
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previous.devfn = previous_unitid << 3;
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}
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last.bus = bus;
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last.devfn = last_unitid << 3;
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/* Set link width and frequency */
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flags = pci_read_config16(&last, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
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cap = pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0);
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if(previous_unitid == 0) { /* the link is back to the host */
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links = pci_read_config16(&previous,
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previous_pos + PCI_HT_CAP_HOST_FREQ_CAP);
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width = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_WIDTH);
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}
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else { /* The link is back up the chain */
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links = pci_read_config16(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ_CAP1);
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width = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1);
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}
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/* Calculate the highest possible frequency */
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links &= flags;
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for(flags = 0x40, count = 6; count; count--, flags >>= 1) {
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if(flags & links) break;
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}
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/* Calculate the highest width */
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width &= cap;
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/* set the present device */
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if(count != pci_read_config8(&last, pos + PCI_HT_CAP_HOST_FREQ)) {
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pci_write_config8(&last, pos + PCI_HT_CAP_HOST_FREQ, count);
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reset_needed = 1;
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}
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if(width != pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1)) {
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pci_write_config8(&last,
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pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, width);
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reset_needed = 1;
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}
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/* set the upstream device */
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if(previous_unitid == 0) { /* the link is back to the host */
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cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_FREQ);
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cap &= 0x0f;
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if(count != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_FREQ, count);
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reset_needed = 1;
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}
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cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_WIDTH + 1);
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if(width != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_HOST_WIDTH + 1, width);
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reset_needed = 1;
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}
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}
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else { /* The link is back up the chain */
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cap = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ1);
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cap &= 0x0f;
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if(count != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_FREQ1, count);
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reset_needed = 1;
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}
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cap = pci_read_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
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if(width != cap) {
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pci_write_config8(&previous,
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previous_pos + PCI_HT_CAP_SLAVE_WIDTH1, width);
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reset_needed = 1;
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}
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}
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break;
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}
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}
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pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
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}
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previous_pos = pos;
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} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
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#endif /* HYPERTRANSPORT_SUPPORT */
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@ -182,7 +182,18 @@
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#define PCI_CAP_ID_HT 0x08
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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/* Hypertransport Registers */
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#define PCI_HT_CAP_SIZEOF 4
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#define PCI_HT_CAP_HOST_WIDTH 6 /* width value & capability */
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#define PCI_HT_CAP_HOST_FREQ 0x09 /* Host frequency */
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#define PCI_HT_CAP_HOST_FREQ_CAP 0x0a /* Host Frequency capability */
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#define PCI_HT_CAP_SLAVE_WIDTH0 6 /* width value & capability */
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#define PCI_HT_CAP_SLAVE_WIDTH1 0x0a /* width value & capability to */
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#define PCI_HT_CAP_SLAVE_FREQ0 0x0d /* Slave frequency from */
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#define PCI_HT_CAP_SLAVE_FREQ1 0x011 /* Slave frequency to */
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#define PCI_HT_CAP_SLAVE_FREQ_CAP0 0x0e /* Frequency capability from */
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#define PCI_HT_CAP_SLAVE_FREQ_CAP1 0x12 /* Frequency capability to */
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/* Power Management Registers */
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@ -150,43 +150,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|0, 0x04, 0x1);
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bus_8131_2, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|1, 0x04, 0x2);
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bus_8131_2, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|2, 0x04, 0x3);
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bus_8131_2, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|3, 0x04, 0x0);
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bus_8131_2, (1<<2)|3, 0x02, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|0, 0x04, 0x2);
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bus_8131_2, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|1, 0x04, 0x3);
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bus_8131_2, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|2, 0x04, 0x0);
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bus_8131_2, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|3, 0x04, 0x1);
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bus_8131_2, (2<<2)|3, 0x02, 0x11);
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/* PCI Slot 3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|0, 0x03, 0x1);
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bus_8131_1, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|1, 0x03, 0x2);
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bus_8131_1, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|2, 0x03, 0x3);
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bus_8131_1, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|3, 0x03, 0x0);
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bus_8131_1, (1<<2)|3, 0x02, 0x10);
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/* PCI Slot 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|0, 0x03, 0x2);
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bus_8131_1, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|1, 0x03, 0x3);
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bus_8131_1, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|2, 0x03, 0x0);
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bus_8131_1, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|3, 0x03, 0x1);
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bus_8131_1, (2<<2)|3, 0x02, 0x11);
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/* PCI Slot 5 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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@ -9,6 +9,28 @@
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static void pcix_init(device_t dev)
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{
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uint16_t word;
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uint8_t byte;
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/* Enable memory write and invalidate ??? */
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byte = pci_read_config8(dev, 0x04);
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byte |= 0x10;
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pci_write_config8(dev, 0x04, byte);
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/* Set drive strength */
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word = pci_read_config16(dev, 0xe0);
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word = 0x0404;
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pci_write_config16(dev, 0xe0, word);
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word = pci_read_config16(dev, 0xe4);
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word = 0x0404;
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pci_write_config16(dev, 0xe4, word);
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/* Set impedance */
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word = pci_read_config16(dev, 0xe8);
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word = 0x0404;
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pci_write_config16(dev, 0xe8, word);
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return;
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}
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