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soc/intel/apollolake: Take advantage of common opregion code 

Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14807
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2016-05-12 19:11:48 -07:00 committed by Aaron Durbin
parent dc4ae11366
commit 868679fe96
3 changed files with 68 additions and 2 deletions
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2
src/soc/intel/apollolake/Kconfig
View File

@ -44,6 +44,8 @@ config CPU_SPECIFIC_OPTIONS
select PLATFORM_USES_FSP2_0
select HAVE_HARD_RESET
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_GFX_OPREGION
select ADD_VBT_DATA_FILE
config TPM_ON_FAST_SPI
bool

19
src/soc/intel/apollolake/chip.c
View File

@ -27,11 +27,15 @@
#include <memrange.h>
#include <soc/iomap.h>
#include <soc/cpu.h>
#include <soc/intel/common/vbt.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include "chip.h"
static void *vbt;
static struct region_device vbt_rdev;
static void pci_domain_set_resources(device_t dev)
{
assign_resources(dev->link_list);
@ -69,6 +73,10 @@ static void soc_init(void *data)
struct range_entry range;
struct global_nvs_t *gnvs;
/* Save VBT info and mapping */
if (locate_vbt(&vbt_rdev) != CB_ERR)
vbt = rdev_mmap_full(&vbt_rdev);
/* TODO: tigten this resource range */
/* TODO: fix for S3 resume, as this would corrupt OS memory */
range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
@ -78,13 +86,19 @@ static void soc_init(void *data)
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
}
static void soc_final(void *data)
{
if (vbt)
rdev_munmap(&vbt_rdev, vbt);
}
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
{
struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = fsp_load_vbt();
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
struct device *dev = NB_DEV_ROOT;
if (!dev || !dev->chip_info) {
@ -111,7 +125,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
struct chip_operations soc_intel_apollolake_ops = {
CHIP_NAME("Intel Apollolake SOC")
.enable_dev = &enable_dev,
.init = &soc_init
.init = &soc_init,
.final = &soc_final
};
static void fsp_notify_dummy(void *arg)

49
src/soc/intel/apollolake/graphics.c
View File

@ -15,12 +15,15 @@
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/pci_ids.h>
#include <soc/intel/common/opregion.h>
static uintptr_t framebuffer_bar = (uintptr_t)NULL;
@ -53,11 +56,57 @@ static void igd_set_resources(struct device *dev)
pci_dev_set_resources(dev);
}
static unsigned long igd_write_opregion(device_t dev, unsigned long current,
struct acpi_rsdp *rsdp)
{
igd_opregion_t *opregion;
uint16_t reg16;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
if (!init_igd_opregion(opregion))
return current;
current += sizeof(igd_opregion_t);
/* TODO Initialize Mailbox 3 */
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
/*
* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler.
*/
pci_write_config32(dev, ASLS, (uintptr_t)opregion);
reg16 = pci_read_config16(dev, SWSCI);
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
pci_write_config16(dev, SWSCI, reg16);
return acpi_align_current(current);
}
static const struct device_operations igd_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = igd_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = pci_dev_init,
.write_acpi_tables = igd_write_opregion,
.enable = DEVICE_NOOP
};