soc/intel/xeon_sp/skx: Hook up microcode blob

TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.

Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/xeon_sp/Kconfig

@@ -57,7 +57,6 @@ config	CPU_SPECIFIC_OPTIONS
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS
-	select MICROCODE_BLOB_NOT_HOOKED_UP
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select FSP_CAR
 	select CPU_INTEL_COMMON_SMM

src/soc/intel/xeon_sp/cpx/Kconfig

@@ -2,6 +2,10 @@
 
 if SOC_INTEL_COOPERLAKE_SP
 
+config SOC_SPECIFIC_OPTIONS
+	def_bool y
+	select MICROCODE_BLOB_NOT_HOOKED_UP
+
 config FSP_HEADER_PATH
 	  string "Location of FSP headers"
 	  depends on MAINBOARD_USES_FSP2_0

src/soc/intel/xeon_sp/skx/Makefile.inc

@@ -29,4 +29,6 @@ ramstage-y += hob_display.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
 
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04
+
 endif ## CONFIG_SOC_INTEL_SKYLAKE_SP