skylake: ACPI: Clean up pch.asl

Clean up the code in pch.asl:
- move all the C header includes into here instead of duplicated
in various ASL files included from here
- move the trap field definition into platform.asl with the method
- alphebetize the includes
- move gpio.asl include into pch.asl
- remove duplicate irqlinks.asl include from lpc.asl

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11530
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/skylake/acpi/gpio.asl

@@ -18,10 +18,6 @@
  * Foundation, Inc.
  */
 
-#include <soc/irq.h>
-#include <soc/iomap.h>
-#include <soc/pcr.h>
-#include <soc/gpio_defs.h>
 
 /* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
 Method (PCRR, 2, Serialized)

src/soc/intel/skylake/acpi/lpc.asl

@@ -19,7 +19,6 @@
  * Foundation, Inc.
  */
 
-#include <soc/iomap.h>
 
 // Intel LPC Bus Device  - 0:1f.0
 
@@ -169,8 +168,6 @@ Device (LPCB)
 		})
 	}
 
-	#include "gpio.asl"
-	#include "irqlinks.asl"
 	#include <acpi/ec.asl>
 	#include <acpi/superio.asl>
 }

src/soc/intel/skylake/acpi/pch.asl

@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
  * Copyright (C) 2015 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -20,38 +20,34 @@
  */
 
 #include <soc/iomap.h>
+#include <soc/irq.h>
+#include <soc/gpio_defs.h>
+#include <soc/gpe.h>
+#include <soc/pcr.h>
 
-Scope (\)
+/* GPIO Controller */
-{
+#include "gpio.asl"
-	/* IO-Trap at 0x800.
-	 * This is the ACPI->SMI communication interface.
-	 */
-	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
-	Field (IO_T, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x8),
-		TRP0, 8		/* IO-Trap at 0x808 */
-	}
-}
 
-/* PCI Express Ports 0:1c.x */
+/* Interrupt Routing */
-#include "pcie.asl"
+#include "irqlinks.asl"
 
-/* USB XHCI 0:14.0 */
+/* LPC 0:1f.0 */
-#include "xhci.asl"
-
-/* LPC Bridge 0:1f.0 */
 #include "lpc.asl"
 
-/* SMBus 0:1f.3 */
+/* PCIE Ports */
-#include "smbus.asl"
+#include "pcie.asl"
+
 
 /* Serial IO */
 #include "serialio.asl"
 
-/* Interrupt Routing */
+/* SMBus 0:1f.3 */
+#include "smbus.asl"
+
+
 #include "itss.asl"
-#include "irqlinks.asl"
+/* USB XHCI 0:14.0 */
+#include "xhci.asl"
 
 Method (_OSC, 4)
 {

src/soc/intel/skylake/acpi/platform.asl

@@ -36,6 +36,16 @@ Field (POST, ByteAcc, Lock, Preserve)
 	DBG0, 8
 }
 
+/* IO-Trap at 0x800.
+ * This is the ACPI->SMI communication interface.
+ */
+OperationRegion (IO_T, SystemIO, 0x800, 0x10)
+Field (IO_T, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x8),
+	TRP0, 8		/* IO-Trap at 0x808 */
+}
+
 /* SMI I/O Trap */
 Method (TRAP, 1, Serialized)
 {

src/soc/intel/skylake/acpi/serialio.asl

@@ -17,7 +17,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc.
  */
-#include <soc/irq.h>
 
 // Intel Serial IO Devices in ACPI Mode