GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add preliminary support for Bachmann electronic OT200 

Linux boots fine :)

Change-Id: Ifda06e5220666534b87f528deae16d8b956c32b3
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1225
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Christian Gmeiner 2012-07-13 11:36:08 +02:00 committed by Patrick Georgi
parent 42b808e889
commit 86f992c38a
8 changed files with 285 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/Kconfig
View File

@ -34,6 +34,8 @@ config VENDOR_AXUS
bool "AXUS"
config VENDOR_AZZA
bool "AZZA"
config VENDOR_BACHMANN
bool "Bachmann electronic"
config VENDOR_BCOM
bool "BCOM"
config VENDOR_BIFFEROS
@ -144,6 +146,7 @@ source "src/mainboard/asus/Kconfig"
source "src/mainboard/avalue/Kconfig"
source "src/mainboard/axus/Kconfig"
source "src/mainboard/azza/Kconfig"
source "src/mainboard/bachmann/Kconfig"
source "src/mainboard/bcom/Kconfig"
source "src/mainboard/bifferos/Kconfig"
source "src/mainboard/biostar/Kconfig"

17
src/mainboard/bachmann/Kconfig Normal file
View File

@ -0,0 +1,17 @@
if VENDOR_BACHMANN
choice
prompt "Mainboard model"
config BOARD_BACHMANN_OT200
bool "OT200"
endchoice
source "src/mainboard/bachmann/ot200/Kconfig"
config MAINBOARD_VENDOR
string
default "Bachmann electronic"
endif # VENDOR_BACHMANN

28
src/mainboard/bachmann/ot200/Kconfig Normal file
View File

@ -0,0 +1,28 @@
if BOARD_BACHMANN_OT200
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_GEODE_LX
select NORTHBRIDGE_AMD_LX
select SOUTHBRIDGE_AMD_CS5536
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_2048
select POWER_BUTTON_DEFAULT_DISABLE
select DRIVERS_I2C_IDREG
config MAINBOARD_DIR
string
default bachmann/ot200
config MAINBOARD_PART_NUMBER
string
default "OT200"
config IRQ_SLOT_COUNT
int
default 6
endif # BOARD_BACHMANN_OT200

23
src/mainboard/bachmann/ot200/chip.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {};

36
src/mainboard/bachmann/ot200/devicetree.cb Normal file
View File

@ -0,0 +1,36 @@
chip northbridge/amd/lx
device pci_domain 0 on
device pci 1.0 on end # Northbridge
device pci 1.1 on end # Graphics
device pci 1.2 on end # AES
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x00000000"
register "lpc_serirq_polarity" = "0x00000000"
register "lpc_serirq_mode" = "0"
register "enable_gpio_int_route" = "0x0C0D0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "1"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
register "unwanted_vpci[0]" = "0" # End of list has a zero
device pci 4.0 on end # Ethernet 0
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
device pci f.7 on end # UOC
end
end
# APIC cluster is late CPU init.
device lapic_cluster 0 on
chip cpu/amd/geode_lx
device lapic 0 on end
end
end
end

68
src/mainboard/bachmann/ot200/irq_tables.c Normal file
View File

@ -0,0 +1,68 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 5
#define PIRQB 9
#define PIRQC 7
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
0x0f << 3, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */
0x2b, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x20, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* CPU */
{0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
{0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, /* ethernet */
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

24
src/mainboard/bachmann/ot200/mainboard.c Normal file
View File

@ -0,0 +1,24 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
struct chip_operations mainboard_ops = {
CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
};

86
src/mainboard/bachmann/ot200/romstage.c Normal file
View File

@ -0,0 +1,86 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Bachmann electronic GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdlib.h>
#include <stdint.h>
#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include "southbridge/amd/cs5536/early_smbus.c"
#include "southbridge/amd/cs5536/early_setup.c"
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
}
#define ManualConf 1 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */
#define PLLMSRlo 0x07de001e
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_lx/cpureginit.c"
#include "cpu/amd/geode_lx/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0}}
};
SystemPreInit();
msr_init();
cs5536_early_setup();
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
/* cs5536_disable_internal_uart: disable them for now, set them
* up later...
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
sdram_initialize(1, memctrl);
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}