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soc/intel/skylake: Enable TraceHub depending on devicetree configuration

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Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.

I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.

Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2020-07-25 10:03:37 +02:00 committed by Michael Niewöhner
parent ffe90c528b
commit 87aecf811d
17 changed files with 3 additions and 17 deletions
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1
src/mainboard/51nb/x210/devicetree.cb
View file

@ -49,7 +49,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/mainboard/google/eve/devicetree.cb
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@ -42,7 +42,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View file

@ -73,7 +73,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/mainboard/google/glados/devicetree.cb
View file

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View file

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View file

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View file

@ -43,7 +43,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View file

@ -48,7 +48,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -38,7 +38,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"

1
src/mainboard/libretrend/lt1000/devicetree.cb
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@ -50,7 +50,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View file

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "0"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
View file

@ -55,7 +55,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View file

@ -35,7 +35,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "0"
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"

1
src/soc/intel/skylake/chip.h
View file

@ -175,7 +175,6 @@ struct soc_intel_skylake_config {
u8 IoBufferOwnership;
/* Trace Hub function */
u8 EnableTraceHub;
u32 TraceHubMemReg0Size;
u32 TraceHubMemReg1Size;

4
src/soc/intel/skylake/romstage/romstage.c
View file

@ -293,7 +293,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
/* DCI and TraceHub configs */
m_t_cfg->PchDciEn = config->PchDciEn;
m_cfg->EnableTraceHub = config->EnableTraceHub;
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
m_cfg->EnableTraceHub = dev ? dev->enabled : 0;
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;