GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Enable SMBus depending on devicetree configuration 

Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.

I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.

Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-07-25 08:40:15 +02:00 committed by Michael Niewöhner
parent 57c8143350
commit ffe90c528b
24 changed files with 4 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/51nb/x210/devicetree.cb
View File

@ -51,7 +51,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/asrock/h110m/devicetree.cb
View File

@ -28,7 +28,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"

1
src/mainboard/facebook/monolith/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
# FSP Configuration
register "EnableAzalia" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "SkipExtGfxScan" = "1"

1
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
View File

@ -32,7 +32,6 @@ chip soc/intel/tigerlake
register "SataEnable" = "1"
register "SataMode" = "0"
register "SataSalpSupport" = "1"
register "SmbusEnable" = "1"
# TODO: the lengths are all MID for right now.
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1

1
src/mainboard/google/eve/devicetree.cb
View File

@ -44,7 +44,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View File

@ -75,7 +75,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/google/glados/devicetree.cb
View File

@ -46,7 +46,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"

1
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View File

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/nami/devicetree.cb
View File

@ -39,7 +39,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View File

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -45,7 +45,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View File

@ -50,7 +50,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "SaImguEnable" = "0"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View File

@ -40,7 +40,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "3"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "1"
register "SaImguEnable" = "1"
register "ScsEmmcEnabled" = "1"

1
src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
View File

@ -23,7 +23,6 @@ chip soc/intel/skylake
register "dptf_enable" = "1"
# FSP Configuration
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"

1
src/mainboard/intel/kunimitsu/devicetree.cb
View File

@ -27,7 +27,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
register "ScsEmmcHs400Enabled" = "1"
register "ScsSdCardEnabled" = "2"

1
src/mainboard/intel/saddlebrook/devicetree.cb
View File

@ -21,7 +21,6 @@ chip soc/intel/skylake
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"

1
src/mainboard/libretrend/lt1000/devicetree.cb
View File

@ -52,7 +52,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/protectli/vault_kbl/devicetree.cb
View File

@ -41,7 +41,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/purism/librem_skl/devicetree.cb
View File

@ -57,7 +57,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View File

@ -37,7 +37,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "EnableTraceHub" = "0"
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"

1
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -7,7 +7,6 @@ chip soc/intel/skylake
register "speed_shift_enable" = "1"
# FSP Configuration
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"

3
src/soc/intel/skylake/chip.h
View File

@ -272,9 +272,6 @@ struct soc_intel_skylake_config {
struct usb3_port_config usb3_ports[10];
u8 SsicPortEnable;
/* SMBus */
u8 SmbusEnable;
/*
* SerialIO device mode selection:
*

6
src/soc/intel/skylake/romstage/romstage.c
View File

@ -272,6 +272,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_skylake_config *config;
const struct device *dev;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
@ -296,8 +297,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size;
m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size;
/* Enable SMBus controller based on config */
m_cfg->SmbusEnable = config->SmbusEnable;
/* Enable SMBus controller */
dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
m_cfg->SmbusEnable = dev ? dev->enabled : 0;
/* Set primary graphic device */
soc_primary_gfx_config_params(m_cfg, config);