mb/google/mancomb: Enable Chrome EC
BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id1617be67bfc5d2f142358ae8a70c3e575a94c6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
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6 changed files with 87 additions and 2 deletions
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@ -9,14 +9,14 @@ config BOARD_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select AMD_SOC_CONSOLE_UART
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select AMD_SOC_CONSOLE_UART
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select BOARD_ROMSIZE_KB_16384
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select BOARD_ROMSIZE_KB_16384
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_CHROMEOS
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select SOC_AMD_CEZANNE
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select SOC_AMD_CEZANNE
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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config CHROMEOS
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config CHROMEOS
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select EC_GOOGLE_CHROMEEC_SWITCHES
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config VBOOT
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config VBOOT
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@ -4,6 +4,7 @@ bootblock-y += bootblock.c
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verstage-y += verstage.c
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verstage-y += verstage.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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20
src/mainboard/google/mancomb/ec.c
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20
src/mainboard/google/mancomb/ec.c
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <amdblocks/gpio_banks.h>
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#include <amdblocks/smi.h>
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#include <ec/google/chromeec/ec.h>
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#include <variant/ec.h>
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void mainboard_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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@ -2,6 +2,7 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <variant/ec.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static void mainboard_configure_gpios(void)
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static void mainboard_configure_gpios(void)
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@ -17,6 +18,7 @@ static void mainboard_configure_gpios(void)
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static void mainboard_init(void *chip_info)
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static void mainboard_init(void *chip_info)
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{
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{
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mainboard_configure_gpios();
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mainboard_configure_gpios();
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mainboard_ec_init();
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}
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}
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static void mainboard_enable(struct device *dev)
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static void mainboard_enable(struct device *dev)
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@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __MAINBOARD_EC_H__
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#define __MAINBOARD_EC_H__
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <baseboard/gpio.h>
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#include <soc/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
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#define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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/* EC can wake from S5 with power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)
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/* EC can wake from S3 with lid, power button or mode change event */
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#define MAINBOARD_EC_S3_WAKE_EVENTS \
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(MAINBOARD_EC_S5_WAKE_EVENTS | EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) \
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| EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Set GPI for SCI */
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#define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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/* Enable EC sync interrupt */
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#define EC_ENABLE_SYNC_IRQ_GPIO
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/* EC sync irq */
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#define EC_SYNC_IRQ GPIO_84
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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#endif /* __MAINBOARD_EC_H__ */
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@ -0,0 +1,3 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/ec.h>
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