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mb/google/guybrush: Enable STT in device tree 

Enable Skin Temperature Tracking with initial configuration settings.

BUG=b:190732595
TEST=Confirm that AGT tool can successfully complete data collection

Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jason Glenesk 2021-06-11 12:09:20 -07:00 committed by Felix Held
parent b2a1480191
commit 87f20739bb
1 changed files with 22 additions and 0 deletions
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22
src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
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@ -48,6 +48,28 @@ chip soc/amd/cezanne
# Enable S0i3 support # Enable S0i3 support
register "s0ix_enable" = "1" register "s0ix_enable" = "1"
# Enable STT support
register "stt_control" = "1"
register "stt_pcb_sensor_count" = "2"
register "stt_min_limit" = "0"
register "stt_m1" = "0x0319"
register "stt_m2" = "0x01A0"
register "stt_m3" = "0"
register "stt_m4" = "0"
register "stt_m5" = "0"
register "stt_m6" = "0"
register "stt_c_apu" = "0xE99F"
register "stt_c_gpu" = "0"
register "stt_c_hs2" = "0"
register "stt_alpha_apu" = "0xCCD"
register "stt_alpha_gpu" = "0"
register "stt_alpha_hs2" = "0"
register "stt_skin_temp_apu" = "0x2D00"
register "stt_skin_temp_gpu" = "0"
register "stt_skin_temp_hs2" = "0"
register "stt_error_coeff" = "0xD"
register "stt_error_rate_coefficient" = "0x8F6"
register "system_configuration" = "2" register "system_configuration" = "2"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |