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geeesh! And this really compiles and even runs? 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-14 16:39:30 +00:00 committed by Stefan Reinauer
parent 4bcfb095b1
commit 8816cdf311
10 changed files with 255 additions and 311 deletions
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115
src/mainboard/via/epia-m700/romstage.c
View File

@ -58,7 +58,7 @@
* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
* http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
*/ */
int acpi_is_wakeup_early_via_vx800(void) static int acpi_is_wakeup_early_via_vx800(void)
{ {
device_t dev; device_t dev;
u16 tmp, result; u16 tmp, result;
@ -94,8 +94,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void enable_mainboard_devices(void) static void enable_mainboard_devices(void)
{ {
device_t dev; device_t dev;
uint16_t values;
#if 0 #if 0
/* /*
* Add and close this switch, since some line cause error, some * Add and close this switch, since some line cause error, some
@ -145,6 +143,8 @@ static void enable_mainboard_devices(void)
#if 0 #if 0
dev = 0; dev = 0;
dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0);
uint16_t values;
values = pci_read_config16(dev, 0xBA); values = pci_read_config16(dev, 0xBA);
values &= ~0xffff; values &= ~0xffff;
values |= 0x5324; values |= 0x5324;
@ -202,68 +202,68 @@ static void enable_shadow_ram(void)
*/ */
static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = {
/* VT3409 no PCI-E */ /* VT3409 no PCI-E */
0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range
0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie
// 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
// Set ROMSIP value by software // Set ROMSIP value by software
/* /*
0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3
0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3
0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl
0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl
0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit
0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status
0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset
0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset
0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status
0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status
0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group
0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group
0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group
0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1
0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2
0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB
0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD
0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0)
0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1)
0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2)
0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3)
*/ */
// CPU Host Bus Control // CPU Host Bus Control
0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
// 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance
// 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access
// 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1
// 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
// 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy
0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer
0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl
// 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3
// 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2
0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3
0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4
// Set APIC and SMRAM // Set APIC and SMRAM
0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control
0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table
}; };
#define USE_VCP 1 /* 0 means "use DVP". */ #define USE_VCP 1 /* 0 means "use DVP". */
@ -383,7 +383,6 @@ void EmbedComInit(void)
/* cache_as_ram.inc jumps to here. */ /* cache_as_ram.inc jumps to here. */
void main(unsigned long bist) void main(unsigned long bist)
{ {
unsigned cpu_reset = 0;
u16 boot_mode; u16 boot_mode;
u8 rambits, Data8, Data; u8 rambits, Data8, Data;
device_t device; device_t device;

5
src/northbridge/via/vx800/detection.c
View File

@ -17,6 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
/* FIXME this should go away */
static const struct mem_controller ctrl = {
.channel0 = {0x50, 0x51},
};
#define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */ #define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */
#define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */ #define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */
#define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */ #define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */

5
src/northbridge/via/vx800/dev_init.c
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@ -166,7 +166,7 @@ Purpose : DRAM initialize according to the bios porting guid
#define EXIST_TEST_PATTERN 0x55555555 #define EXIST_TEST_PATTERN 0x55555555
#define NOT_EXIST_TEST_PATTERN 0xAAAAAAAA #define NOT_EXIST_TEST_PATTERN 0xAAAAAAAA
BOOLEAN ChkForExistLowBank(void) static BOOLEAN ChkForExistLowBank(void)
{ {
u32 *Address, data32; u32 *Address, data32;
@ -207,9 +207,6 @@ BOOLEAN ChkForExistLowBank(void)
return TRUE; return TRUE;
} }
void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr);
void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr);
void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr)
{ {
u8 shift, idx; u8 shift, idx;

4
src/northbridge/via/vx800/dram_init.h
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@ -121,10 +121,6 @@ struct mem_controller {
u8 channel0[MAX_DIMMS]; u8 channel0[MAX_DIMMS];
}; };
static const struct mem_controller ctrl = {
.channel0 = {0x50, 0x51},
};
typedef struct _DRAM_CONFIG_DATA { typedef struct _DRAM_CONFIG_DATA {
u8 DramClk; u8 DramClk;
u8 DramTiming; u8 DramTiming;

10
src/northbridge/via/vx800/drdy_bl.c
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@ -404,10 +404,7 @@ static const u8 PT894_64bit_DELAYMD1_RCONV0[6][6][PT894_RDRDY_TBL_Width] =
void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
{ {
u8 Data, CL, RDRPH; u8 Data;
u8 CpuFreq, DramFreq;
u8 ProgData[PT894_RDRDY_TBL_Width];
/* /*
this function has 3 switchs, correspond to 3 level of Drdy setting. this function has 3 switchs, correspond to 3 level of Drdy setting.
0:Slowest, 1:Default, 2:Optimize 0:Slowest, 1:Default, 2:Optimize
@ -464,6 +461,9 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
} }
#endif #endif
#if 0 // 2:Optimize #if 0 // 2:Optimize
u8 CpuFreq, DramFreq;
u8 CL, RDRPH;
//CL :reg6x[2:0] //CL :reg6x[2:0]
Data = pci_read_config8(MEMCTRL, 0x62); Data = pci_read_config8(MEMCTRL, 0x62);
CL = Data & 0x07; CL = Data & 0x07;
@ -484,6 +484,8 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH)
DelayMode &= 0x01; DelayMode &= 0x01;
u8 ProgData[PT894_RDRDY_TBL_Width];
//In 364, there is no 128 bit //In 364, there is no 128 bit
if (DelayMode == 1) { // DelayMode 1 if (DelayMode == 1) { // DelayMode 1
u8 Index; u8 Index;

363
src/northbridge/via/vx800/examples/chipset_init.c
View File

@ -43,12 +43,12 @@ static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = {
{0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC {0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC
///// SPI-BAR. ///// SPI-BAR.
//// SPI_BASE_ADDRESS = 0xFED1 0000 //// SPI_BASE_ADDRESS = 0xFED1 0000
0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00, {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00},
0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1, {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1},
0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE, {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE},
// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00,//this , for the different macro // {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro
// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1, // {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1},
// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE, // {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE},
///// End of 2008-04-17 ///// End of 2008-04-17
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
@ -60,191 +60,184 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage2InitTable[] = {
// D0F2~D0F3 is configured by MemoryInit Peim // D0F2~D0F3 is configured by MemoryInit Peim
// D0F4: NB PMU // D0F4: NB PMU
0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB, { 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB },
0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05, { 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 },
0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8, { 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 },
0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF, { 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF },
0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC, { 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC },
0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19, { 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 },
0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00, { 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 },
0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF, { 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF },
0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF, { 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF },
0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC, { 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC },
0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80, { 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 },
0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0, { 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 },
0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6, { 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 },
0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80, { 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 },
0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20, { 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 },
// D0F5: NB APIC, PXPTRF and MSGC // D0F5: NB APIC, PXPTRF and MSGC
//Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex. //Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex.
//Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase. //Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase.
//Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase. //Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase.
0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00, { 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 },
0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80, { 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 },
0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04, { 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 },
0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00, { 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 },
0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02, { 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 },
0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00, { 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 },
0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06, { 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 },
0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. { 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 }, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1.
0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00, //Set RVC1RPSW, RVC1RQ1T to 1. { 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 }, //Set RVC1RPSW, RVC1RQ1T to 1.
0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81, { 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 },
0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28, { 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 },
0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0, { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 },
0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01, // RWAKEEN { 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 }, // RWAKEEN
// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN //{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN
0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20, { 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 },
0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00, //RP2P1ABORT { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 }, //RP2P1ABORT
// fine-tune // fine-tune
// If no settings, C7 will hang or reboot in XP, but CN will not. // If no settings, C7 will hang or reboot in XP, but CN will not.
0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00, { 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 },
0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03, { 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 },
0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00, { 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 },
0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00, { 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 },
0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01, { 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 },
0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10, { 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 },
0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08, { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 },
0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04, // ACPI Base addr { 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 }, // ACPI Base addr
0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI { 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 }, // APIC MSI
0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI { 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 }, // APIC MSI
//GTL //GTL
0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66, { 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 },
0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33, { 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 },
0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33, { 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 },
0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33, { 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 },
0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33, { 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 },
0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20, { 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 },
0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00, { 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 },
// End of Table // End of Table
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
}; };
static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = {
// D17F0: LPC // D17F0: LPC
0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44, // Enable I/O Recovery Time, 4D0/4D1 Support { 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 }, // Enable I/O Recovery Time, 4D0/4D1 Support
0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD { 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 }, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD
0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B, // RENDTX, ENWBTO, ENRBTO { 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B }, // RENDTX, ENWBTO, ENRBTO
// 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10, // It is related to INTH# //{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 }, // It is related to INTH#
//0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C, //RMRPW, RIRPW // Reserved in 409 by Eric //{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C }, //RMRPW, RIRPW // Reserved in 409 by Eric
// Internal RTC, Mouse, Keyboard // set in PEI by Eric // Internal RTC, Mouse, Keyboard // set in PEI by Eric
//0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D, // Enable Internal RTC, Internal PS2 Mouse/Keyboard //{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D }, // Enable Internal RTC, Internal PS2 Mouse/Keyboard
// RTC // RTC
0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01, //RTC Rx32 Map to Centrury Byte { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 }, //RTC Rx32 Map to Centrury Byte
// 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02, // RDMEGAS //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 }, // RDMEGAS
//0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric //{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 }, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric
// Serial IRQ // set in PEI by Eric // Serial IRQ // set in PEI by Eric
//0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. //{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 }, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock.
// Enable 4D0h/4D1h Port // Enable 4D0h/4D1h Port
//0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04, // EISAXT // set in PEI by Eric //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 }, // EISAXT // set in PEI by Eric
// Config ROM Interface // Config ROM Interface
// Enable SPI/Set SPI Memory Base Address // Enable SPI/Set SPI Memory Base Address
// It is initialized in PEI Phase // It is initialized in PEI Phase
// Subsystem ID/Vendor ID Back Door // Subsystem ID/Vendor ID Back Door
0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06, { 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 },
0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11, { 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 },
0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09, { 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 },
0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34, { 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 },
0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40, { 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 },
0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51, // Orgin value 0x53, modify for 409 by Eric { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 }, // Orgin value 0x53, modify for 409 by Eric
0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01, { 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 },
0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable { 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 }, // Setting PCI device enable
0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable { 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 }, // Setting PCI device enable
0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable { 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 }, // Setting HDAC enable
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
}; };
static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = {
//PCI1 Programming Sequence //PCI1 Programming Sequence
//(1)Configure D17F7 //(1)Configure D17F7
0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03, { 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 },
0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08, // Reserved in 409 by Eric { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric
0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41, //RENPPB, RP2CFLSH { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH
0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion
// 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured.
//0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista)
//(2)Configure D19F0 //(2)Configure D19F0
0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07, { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 },
//(3)Performance Recommended Setting //(3)Performance Recommended Setting
//Save Power //Save Power
0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01, { 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 },
0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E, { 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E },
0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00, { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 },
//Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance
0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82, { 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 },
0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0, { 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 },
0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE, { 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE },
//Cycle Control //Cycle Control
0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01, { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 },
0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C, { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C },
//Arbitration control //Arbitration control
0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F, { 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F },
0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0, { 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 },
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
}; };
static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = {
{ 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 }, //RVWREQ, ROABKDOOR
0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08, //RVWREQ, ROABKDOOR
//CCA's Register Programming sequence //CCA's Register Programming sequence
0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08, //Config Azalia's upstream cycle high priority and other low priority { 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 }, //Config Azalia's upstream cycle high priority and other low priority
0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80, //Disable bypass asynchronous circuit { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 }, //Disable bypass asynchronous circuit
0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11, // Set SM Internal Device and HDAC Occupy Timer { 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 }, // Set SM Internal Device and HDAC Occupy Timer
0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11, // Set SM Internal Device and HDAC Promote Timer { 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 }, // Set SM Internal Device and HDAC Promote Timer
0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02, //Use SB internal devices's original REQ { 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 }, //Use SB internal devices's original REQ
0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 }, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle
0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C, //RLCKXP2C, RFSBVK. { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C }, //RLCKXP2C, RFSBVK.
0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00, //RBLKAPIC, RAZC3 { 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 }, //RBLKAPIC, RAZC3
0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02, //RNMIFSB, RFSBVK { 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 }, //RNMIFSB, RFSBVK
0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme { 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 }, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme
0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00, //Let CCA use dynamic clock. { 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 }, //Let CCA use dynamic clock.
//The CCA is also relate to D17F0 //The CCA is also relate to D17F0
// 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00, //Disable CCA Test Mode //{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 }, //Disable CCA Test Mode
0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric { 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 }, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
}; };
static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = { static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = {
//{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode
// 0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05, //set to native mode {0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07},
0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07, //{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F},
//0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F,
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table
}; };
static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = {
0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00, { 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 },
0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00, { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 },
0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00, { 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 },
0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40, { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 },
0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04, { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 },
//0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F, //{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F },
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table
}; };
void AcpiInit(void) void AcpiInit(void)
{ {
device_t_raw rawdevice = 0; device_t_raw rawdevice = 0;
@ -268,10 +261,8 @@ void AcpiInit(void)
// Close all SMI/Io Traps // Close all SMI/Io Traps
outb(0x00, VX800_ACPI_IO_BASE + 0x42); outb(0x00, VX800_ACPI_IO_BASE + 0x42);
} }
void Stage2NbInit(void) void Stage2NbInit(void)
{ {
device_t_raw rawdevice = 0; device_t_raw rawdevice = 0;
@ -290,7 +281,6 @@ void Stage2NbInit(void)
//vx855 NB no pcie bus //vx855 NB no pcie bus
//vx855 NB no apic //vx855 NB no apic
} }
void IDECSupportOption(u8 sbchiprev) void IDECSupportOption(u8 sbchiprev)
@ -313,7 +303,6 @@ void InitIDEC(u8 sbchiprev)
IDECSupportOption(sbchiprev); IDECSupportOption(sbchiprev);
} }
void InitUHCI(u8 Number, u8 bEnable) void InitUHCI(u8 Number, u8 bEnable)
{ {
u8 Mask, Value; u8 Mask, Value;
@ -374,25 +363,24 @@ void InitUHCI(u8 Number, u8 bEnable)
static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = {
//EHCI //EHCI
0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0, { 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 },
0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80, { 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 },
0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E, { 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E },
0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68, { 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 },
0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69, { 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 },
0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94, { 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 },
0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00, { 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 },
0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A, { 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A },
0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89, { 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 },
0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03, { 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 },
0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A, { 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A },
0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00, { 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 },
0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00, { 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 },
0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00, { 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 },
0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00, { 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 },
0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01, { 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 },
0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11, { 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 },
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table
}; };
void InitEHCI(u8 Number, u8 bEnable) void InitEHCI(u8 Number, u8 bEnable)
@ -483,23 +471,23 @@ void HpetInit(void)
static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = {
// Power Management // Power Management
0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20, { 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 },
0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00, { 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 },
0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18, { 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 },
//Miscellaneous Configuration 1 //Miscellaneous Configuration 1
0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28, { 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 },
0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1, { 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 },
0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10, { 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 },
0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2, { 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 },
//Voltage Change Function Enable //Voltage Change Function Enable
0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21, { 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 },
//Internal PCIe and NM PLL Control //Internal PCIe and NM PLL Control
0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA, { 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA },
0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80, { 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 },
{0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table
}; };
void InitPMU(u8 sbchiprev) void InitPMU(u8 sbchiprev)
@ -589,7 +577,6 @@ void Stage2SbInit(void)
} }
void init_VIA_chipset(void) void init_VIA_chipset(void)
{ {
printk(BIOS_DEBUG, "In: init_VIA_chipset\n"); printk(BIOS_DEBUG, "In: init_VIA_chipset\n");
@ -633,7 +620,6 @@ void hardwaremain(int boot_complete)
printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
#if 0 #if 0
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80);
pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20);
pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5,
@ -656,7 +642,6 @@ void hardwaremain(int boot_complete)
printk(BIOS_INFO, "=================SB 50h=%02x \n", printk(BIOS_INFO, "=================SB 50h=%02x \n",
pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50)); pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50));
/* FIXME: Is there a better way to handle this? */ /* FIXME: Is there a better way to handle this? */
init_timer(); init_timer();
printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
@ -690,9 +675,7 @@ void hardwaremain(int boot_complete)
y = 0; y = 0;
for (; y < 16; y++) { for (; y < 16; y++) {
printk(BIOS_INFO, "%02x ", printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
(0, 0x10, 4),
x * 16 + y));
} }
printk(BIOS_INFO, "\n"); printk(BIOS_INFO, "\n");
} }
@ -710,9 +693,7 @@ void hardwaremain(int boot_complete)
y = 0; y = 0;
for (; y < 16; y++) { for (; y < 16; y++) {
printk(BIOS_INFO, "%02x ", printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
(0, 0x10, 4),
x * 16 + y));
} }
printk(BIOS_INFO, "\n"); printk(BIOS_INFO, "\n");
} }
@ -722,7 +703,6 @@ void hardwaremain(int boot_complete)
post_code(0x89); post_code(0x89);
printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__);
// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); // pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571);
#if 0 #if 0
@ -732,17 +712,13 @@ void hardwaremain(int boot_complete)
y = 0; y = 0;
for (; y < 16; y++) { for (; y < 16; y++) {
printk(BIOS_INFO, "%02x ", printk(BIOS_INFO, "%02x ",
pci_rawread_config8(PCI_RAWDEV pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y));
(0, 0x10, 4),
x * 16 + y));
} }
printk(BIOS_INFO, "\n"); printk(BIOS_INFO, "\n");
} }
#endif #endif
#if 0 #if 0
y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d);
y &= 0x0f; y &= 0x0f;
y |= 0x40; y |= 0x40;
@ -750,8 +726,6 @@ void hardwaremain(int boot_complete)
#endif #endif
#if 0 #if 0
static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD }; static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD };
static const d0f2pcitable[16 * 7 + 1] = { static const d0f2pcitable[16 * 7 + 1] = {
0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09, 0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09,
@ -911,7 +885,6 @@ void hardwaremain(int boot_complete)
0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00,
}; };
#define OPTION_1 1 #define OPTION_1 1
#define NOOPTION_1 1 #define NOOPTION_1 1
#ifdef OPTION_1 #ifdef OPTION_1
@ -943,24 +916,19 @@ void hardwaremain(int boot_complete)
}; };
#endif #endif
u8 i; u8 i;
/* error form ---- but add the chance to resume /* error form ---- but add the chance to resume
for(i=0;i<5;i++){ for(i=0;i<5;i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]);
} }
*/ */
/* RO reg /* RO reg
for(i=0;i<5;i++){ for(i=0;i<5;i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]);
} }
*/ */
//boot ok, resume still err in linux //boot ok, resume still err in linux
#if 1 #if 1
for (i = 0; i < 9; i++) { for (i = 0; i < 9; i++) {
@ -1052,11 +1020,7 @@ for(i=0;i<5;i++){
//d15f0 //d15f0
#if 1 #if 1
pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect.
pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2);
pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2); pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2);
@ -1077,8 +1041,6 @@ for(i=0;i<5;i++){
pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80);
#endif #endif
#if 1 #if 1
//before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok
// for(i=0;i<192;i++){ // for(i=0;i<192;i++){
@ -1094,7 +1056,6 @@ for(i=0;i<5;i++){
d11f0pcitable[i]); d11f0pcitable[i]);
} }
for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40,
d11f0pcitable[i]); d11f0pcitable[i]);
@ -1225,7 +1186,6 @@ for(i=0;i<5;i++){
pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72,
PCI_DEVICE_ID_VIA_VX855_LPC); PCI_DEVICE_ID_VIA_VX855_LPC);
//boot ok, resume still err in linux //boot ok, resume still err in linux
for (i = 0; i < 192; i++) { for (i = 0; i < 192; i++) {
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40,
@ -1240,17 +1200,12 @@ for(i=0;i<5;i++){
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02);
pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f);
#endif #endif
pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20);
pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31); pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31);
#ifdef OPTION_1 #ifdef OPTION_1
pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00);
#endif #endif
#endif #endif
u8 i911; u8 i911;
@ -1262,10 +1217,9 @@ for(i=0;i<5;i++){
i911 |= 0x01; i911 |= 0x01;
pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911); pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911);
#if 1 #if 1
struct device *dev; struct device *dev;
printk(BIOS_INFO, "=========zjldump all devices...\n"); printk(BIOS_INFO, "========= dump all devices...\n");
for (dev = all_devices; dev; dev = dev->next) { for (dev = all_devices; dev; dev = dev->next) {
if (dev->path.type == DEVICE_PATH_PCI) { if (dev->path.type == DEVICE_PATH_PCI) {
printk(BIOS_DEBUG, "%s dump\n", dev_path(dev)); printk(BIOS_DEBUG, "%s dump\n", dev_path(dev));
@ -1274,25 +1228,14 @@ for(i=0;i<5;i++){
y = 0; y = 0;
for (; y < 16; y++) { for (; y < 16; y++) {
printk(BIOS_INFO, "%02x ", printk(BIOS_INFO, "%02x ",
pci_read_config8(dev, pci_read_config8(dev, x * 16 + y));
x *
16 +
y));
} }
printk(BIOS_INFO, "\n"); printk(BIOS_INFO, "\n");
} }
} }
printk(BIOS_INFO, "\n"); printk(BIOS_INFO, "\n");
} }
#endif #endif
//pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);//
// pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);///
} }

52
src/northbridge/via/vx800/pci_rawops.h
View File

@ -37,13 +37,16 @@ struct VIA_PCI_REG_INIT_TABLE {
u8 Mask; u8 Mask;
u8 Value; u8 Value;
}; };
typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
#warning "FIXME: get rid of this extra copy of pci access functions."
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore * We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access * Before that We need to use %gs, and leave %fs to other RAM access
*/ */
u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) static u8 pci_io_rawread_config8(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -56,14 +59,14 @@ u8 pci_io_rawread_config8(device_t_raw dev, unsigned where)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) static u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = dev | where; addr = dev | where;
return read8x(addr); return read8x(addr);
} }
#endif #endif
u8 pci_rawread_config8(device_t_raw dev, unsigned where) static u8 pci_rawread_config8(device_t_raw dev, unsigned where)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config8(dev, where); return pci_mmio_rawread_config8(dev, where);
@ -72,7 +75,7 @@ u8 pci_rawread_config8(device_t_raw dev, unsigned where)
#endif #endif
} }
u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) static u16 pci_io_rawread_config16(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -85,7 +88,7 @@ u16 pci_io_rawread_config16(device_t_raw dev, unsigned where)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) static u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = dev | where; addr = dev | where;
@ -93,7 +96,7 @@ u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
} }
#endif #endif
u16 pci_rawread_config16(device_t_raw dev, unsigned where) static u16 pci_rawread_config16(device_t_raw dev, unsigned where)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config16(dev, where); return pci_mmio_rawread_config16(dev, where);
@ -102,7 +105,7 @@ u16 pci_rawread_config16(device_t_raw dev, unsigned where)
#endif #endif
} }
u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) static u32 pci_io_rawread_config32(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -115,7 +118,7 @@ u32 pci_io_rawread_config32(device_t_raw dev, unsigned where)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) static u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
{ {
unsigned addr; unsigned addr;
addr = dev | where; addr = dev | where;
@ -123,7 +126,7 @@ u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
} }
#endif #endif
u32 pci_rawread_config32(device_t_raw dev, unsigned where) static u32 pci_rawread_config32(device_t_raw dev, unsigned where)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config32(dev, where); return pci_mmio_rawread_config32(dev, where);
@ -132,7 +135,7 @@ u32 pci_rawread_config32(device_t_raw dev, unsigned where)
#endif #endif
} }
void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) static void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -145,7 +148,7 @@ void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) static void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{ {
unsigned addr; unsigned addr;
addr = dev | where; addr = dev | where;
@ -153,7 +156,7 @@ void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
} }
#endif #endif
void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) static void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config8(dev, where, value); pci_mmio_rawwrite_config8(dev, where, value);
@ -162,7 +165,7 @@ void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
#endif #endif
} }
void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) static void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -175,7 +178,7 @@ void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, static void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where,
u16 value) u16 value)
{ {
unsigned addr; unsigned addr;
@ -184,7 +187,7 @@ void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where,
} }
#endif #endif
void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) static void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config16(dev, where, value); pci_mmio_rawwrite_config16(dev, where, value);
@ -193,7 +196,7 @@ void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
#endif #endif
} }
void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) static void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
{ {
unsigned addr; unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0 #if CONFIG_PCI_IO_CFG_EXT == 0
@ -206,8 +209,7 @@ void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
} }
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, static void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
u32 value)
{ {
unsigned addr; unsigned addr;
addr = dev | where; addr = dev | where;
@ -215,7 +217,7 @@ void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where,
} }
#endif #endif
void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) static void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
{ {
#if CONFIG_MMCONF_SUPPORT #if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config32(dev, where, value); pci_mmio_rawwrite_config32(dev, where, value);
@ -224,7 +226,7 @@ void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
#endif #endif
} }
void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) static void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask)
{ {
u8 data = pci_rawread_config8(dev, where); u8 data = pci_rawread_config8(dev, where);
data &= (~mask); data &= (~mask);
@ -232,7 +234,7 @@ void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask)
pci_rawwrite_config8(dev, where, data); pci_rawwrite_config8(dev, where, data);
} }
void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) static void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask)
{ {
u16 data = pci_rawread_config16(dev, where); u16 data = pci_rawread_config16(dev, where);
data &= (~mask); data &= (~mask);
@ -240,7 +242,7 @@ void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mas
pci_rawwrite_config16(dev, where, data); pci_rawwrite_config16(dev, where, data);
} }
void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) static void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask)
{ {
u32 data = pci_rawread_config32(dev, where); u32 data = pci_rawread_config32(dev, where);
data &= (~mask); data &= (~mask);
@ -248,7 +250,7 @@ void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mas
pci_rawwrite_config32(dev, where, data); pci_rawwrite_config32(dev, where, data);
} }
void io_rawmodify_config8(u16 where, u8 orval, u8 mask) static void io_rawmodify_config8(u16 where, u8 orval, u8 mask)
{ {
u8 data = inb(where); u8 data = inb(where);
data &= (~mask); data &= (~mask);
@ -256,8 +258,8 @@ void io_rawmodify_config8(u16 where, u8 orval, u8 mask)
outb(data, where); outb(data, where);
} }
void via_pci_inittable(u8 chipversion, static void via_pci_inittable(u8 chipversion,
struct VIA_PCI_REG_INIT_TABLE *initdata) const struct VIA_PCI_REG_INIT_TABLE *initdata)
{ {
u8 i = 0; u8 i = 0;
device_t_raw devbxdxfx; device_t_raw devbxdxfx;

2
src/northbridge/via/vx800/uma_ram_setting.c
View File

@ -71,7 +71,7 @@ void SetUMARam(void)
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0); device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0);
u8 ByteVal, temp; u8 ByteVal, temp;
UMARAM *pUMARamTable; const UMARAM *pUMARamTable;
u16 UmaSize; u16 UmaSize;
u8 SLD0F3Val, SLD1F0Val, VgaPortVal; u8 SLD0F3Val, SLD1F0Val, VgaPortVal;
u32 RamSize, SLBase, Tmp; u32 RamSize, SLBase, Tmp;

8
src/northbridge/via/vx800/vx800_early_smbus.c
View File

@ -244,14 +244,14 @@ static void enable_smbus(void)
* be created just for it. If some other chip needs/wants it, we can * be created just for it. If some other chip needs/wants it, we can
* worry about it then. * worry about it then.
* *
* @param ctrl The memory controller and SMBus addresses. * @param mem_ctrl The memory controller and SMBus addresses.
*/ */
void smbus_fixup(const struct mem_controller *ctrl) static void smbus_fixup(const struct mem_controller *mem_ctrl)
{ {
int i, ram_slots, current_slot = 0; int i, ram_slots, current_slot = 0;
u8 result = 0; u8 result = 0;
ram_slots = ARRAY_SIZE(ctrl->channel0); ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
if (!ram_slots) { if (!ram_slots) {
print_err("smbus_fixup() thinks there are no RAM slots!\n"); print_err("smbus_fixup() thinks there are no RAM slots!\n");
return; return;
@ -272,7 +272,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
if (current_slot > ram_slots) if (current_slot > ram_slots)
current_slot = 0; current_slot = 0;
result = get_spd_data(ctrl->channel0[current_slot], result = get_spd_data(mem_ctrl->channel0[current_slot],
SPD_MEMORY_TYPE); SPD_MEMORY_TYPE);
current_slot++; current_slot++;
PRINT_DEBUG("."); PRINT_DEBUG(".");

2
src/southbridge/via/k8t890/k8t890_early_car.c
View File

@ -34,7 +34,7 @@
/* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */
static ldtreg[3] = {0x86, 0xa6, 0xc6}; static u8 ldtreg[3] = {0x86, 0xa6, 0xc6};
/* This functions sets KT890 link frequency and width to same values as /* This functions sets KT890 link frequency and width to same values as
* it has been setup on K8 side, by AMD NB init. * it has been setup on K8 side, by AMD NB init.