GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

src: Retype option API to use unsigned integers

Browse source 
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.

Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Angel Pons 2021-04-26 17:10:28 +02:00 committed by Felix Held
parent a2cf34129f
commit 88dcb3179b
58 changed files with 113 additions and 113 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/console/init.c
View file

@ -26,7 +26,7 @@ static void init_log_level(void)
console_loglevel = get_console_loglevel();
if (!FIRST_CONSOLE)
console_loglevel = get_int_option("debug_level", console_loglevel);
console_loglevel = get_uint_option("debug_level", console_loglevel);
}
int console_log_level(int msg_level)

2
src/cpu/intel/hyperthreading/intel_sibling.c
View file

@ -21,7 +21,7 @@ void intel_sibling_init(struct device *cpu)
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
disable_siblings = get_int_option("hyper_threading", disable_siblings);
disable_siblings = get_uint_option("hyper_threading", disable_siblings);
}
result = cpuid(1);
/* Is hyperthreading supported */

2
src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c
View file

@ -25,7 +25,7 @@ static void lenovo_hybrid_graphics_enable(struct device *dev)
return;
}
mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
if (mode == HYBRID_GRAPHICS_DISCRETE) {
printk(BIOS_DEBUG, "Hybrid graphics:"

2
src/drivers/lenovo/hybrid_graphics/romstage.c
View file

@ -39,7 +39,7 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
return;
}
mode = get_int_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
mode = get_uint_option("hybrid_graphics_mode", HYBRID_GRAPHICS_DEFAULT_GPU);
if (mode == HYBRID_GRAPHICS_DISCRETE) {
printk(BIOS_DEBUG, "Hybrid graphics:"

10
src/ec/kontron/it8516e/ec.c
View file

@ -133,13 +133,13 @@ static void it8516e_set_fan_from_options(const config_t *const config,
u8 fan_max = config->default_fan_max[fan_idx];
fanX_mode[3] = '1' + fan_idx;
fan_mode = get_int_option(fanX_mode, fan_mode);
fan_mode = get_uint_option(fanX_mode, fan_mode);
if (!fan_mode)
fan_mode = IT8516E_MODE_AUTO;
it8516e_set_fan_mode(fan_idx, fan_mode);
fanX_target[3] = '1' + fan_idx;
fan_target = get_int_option(fanX_target, fan_target);
fan_target = get_uint_option(fanX_target, fan_target);
switch (fan_mode) {
case IT8516E_MODE_AUTO:
printk(BIOS_DEBUG,
@ -173,8 +173,8 @@ static void it8516e_set_fan_from_options(const config_t *const config,
fanX_min[3] = '1' + fan_idx;
fanX_max[3] = '1' + fan_idx;
fan_min = get_int_option(fanX_min, fan_min);
fan_max = get_int_option(fanX_max, fan_max);
fan_min = get_uint_option(fanX_min, fan_min);
fan_max = get_uint_option(fanX_max, fan_max);
if (!fan_max || fan_max > 100) /* Constrain fan_max to 100% */
fan_max = 100;
@ -202,7 +202,7 @@ static void it8516e_pm2_init(struct device *dev)
ec_set_ports(find_resource(dev, PNP_IDX_IO1)->base,
find_resource(dev, PNP_IDX_IO0)->base);
u8 systemp_type = get_int_option("systemp_type", config->default_systemp);
u8 systemp_type = get_uint_option("systemp_type", config->default_systemp);
if (systemp_type >= IT8516E_SYSTEMP_LASTPLUSONE)
systemp_type = IT8516E_SYSTEMP_NONE;
it8516e_set_systemp_type(systemp_type);

2
src/ec/lenovo/h8/bluetooth.c
View file

@ -48,5 +48,5 @@ bool h8_has_bdc(const struct device *dev)
*/
bool h8_bluetooth_nv_enable(void)
{
return get_int_option("bluetooth", true);
return get_uint_option("bluetooth", true);
}

22
src/ec/lenovo/h8/h8.c
View file

@ -243,7 +243,7 @@ static void h8_enable(struct device *dev)
reg8 = conf->config1;
if (conf->has_keyboard_backlight) {
/* Default to both backlights */
reg8 = (reg8 & 0xf3) | ((get_int_option("backlight", 0) & 0x3) << 2);
reg8 = (reg8 & 0xf3) | ((get_uint_option("backlight", 0) & 0x3) << 2);
}
ec_write(H8_CONFIG1, reg8);
ec_write(H8_CONFIG2, conf->config2);
@ -253,14 +253,14 @@ static void h8_enable(struct device *dev)
beepmask1 = conf->beepmask1;
if (conf->has_power_management_beeps) {
if (get_int_option("power_management_beeps", 1) == 0) {
if (get_uint_option("power_management_beeps", 1) == 0) {
beepmask0 = 0x00;
beepmask1 = 0x00;
}
}
if (conf->has_power_management_beeps) {
if (get_int_option("low_battery_beep", 1))
if (get_uint_option("low_battery_beep", 1))
beepmask0 |= 2;
else
beepmask0 &= ~2;
@ -292,14 +292,14 @@ static void h8_enable(struct device *dev)
ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
h8_usb_always_on_enable(get_int_option("usb_always_on", 0));
h8_usb_always_on_enable(get_uint_option("usb_always_on", 0));
h8_wlan_enable(get_int_option("wlan", 1));
h8_wlan_enable(get_uint_option("wlan", 1));
h8_trackpoint_enable(1);
h8_usb_power_enable(1);
unsigned int volume = get_int_option("volume", ~0);
unsigned int volume = get_uint_option("volume", ~0);
if (volume <= 0xff && !acpi_is_wakeup_s3())
ec_write(H8_VOLUME_CONTROL, volume);
@ -311,16 +311,16 @@ static void h8_enable(struct device *dev)
h8_wwan_enable(val);
if (conf->has_uwb)
h8_uwb_enable(get_int_option("uwb", 1));
h8_uwb_enable(get_uint_option("uwb", 1));
h8_fn_ctrl_swap(get_int_option("fn_ctrl_swap", 0));
h8_fn_ctrl_swap(get_uint_option("fn_ctrl_swap", 0));
h8_sticky_fn(get_int_option("sticky_fn", 0));
h8_sticky_fn(get_uint_option("sticky_fn", 0));
if (CONFIG(H8_HAS_PRIMARY_FN_KEYS))
f1_to_f12_as_primary(get_int_option("f1_to_f12_as_primary", 1));
f1_to_f12_as_primary(get_uint_option("f1_to_f12_as_primary", 1));
h8_charge_priority(get_int_option("first_battery", PRIMARY_BATTERY));
h8_charge_priority(get_uint_option("first_battery", PRIMARY_BATTERY));
h8_set_audio_mute(0);
h8_mb_init();

2
src/ec/lenovo/h8/wwan.c
View file

@ -46,5 +46,5 @@ bool h8_has_wwan(const struct device *dev)
*/
bool h8_wwan_nv_enable(void)
{
return get_int_option("wwan", true);
return get_uint_option("wwan", true);
}

4
src/ec/lenovo/pmh7/pmh7.c
View file

@ -117,9 +117,9 @@ static void enable_dev(struct device *dev)
pmh7_backlight_enable(conf->backlight_enable);
pmh7_dock_event_enable(conf->dock_event_enable);
pmh7_touchpad_enable(get_int_option("touchpad", 1));
pmh7_touchpad_enable(get_uint_option("touchpad", 1));
pmh7_trackpoint_enable(get_int_option("trackpoint", 1));
pmh7_trackpoint_enable(get_uint_option("trackpoint", 1));
printk(BIOS_INFO, "PMH7: ID %02x Revision %02x\n",
pmh7_register_read(EC_LENOVO_PMH7_REG_ID),

6
src/include/option.h
View file

@ -10,7 +10,7 @@ void sanitize_cmos(void);
enum cb_err cmos_set_option(const char *name, void *val);
enum cb_err cmos_get_option(void *dest, const char *name);
static inline enum cb_err set_int_option(const char *name, int value)
static inline enum cb_err set_uint_option(const char *name, unsigned int value)
{
if (CONFIG(USE_OPTION_TABLE))
return cmos_set_option(name, &value);
@ -18,10 +18,10 @@ static inline enum cb_err set_int_option(const char *name, int value)
return CB_CMOS_OTABLE_DISABLED;
}
static inline int get_int_option(const char *name, const int fallback)
static inline int get_uint_option(const char *name, const unsigned int fallback)
{
if (CONFIG(USE_OPTION_TABLE)) {
int value = 0;
unsigned int value = 0;
if (cmos_get_option(&value, name) == CB_SUCCESS)
return value;
}

4
src/mainboard/asus/am1i-a/BiosCallOuts.c
View file

@ -87,7 +87,7 @@ void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_
FchParams_reset->Mode = 6;
/* Read SATA speed setting from CMOS */
FchParams_reset->SataSetMaxGen2 = get_int_option("sata_speed", 0);
FchParams_reset->SataSetMaxGen2 = get_uint_option("sata_speed", 0);
printk(BIOS_DEBUG, "Force SATA 3Gbps mode = %x\n", FchParams_reset->SataSetMaxGen2);
}
@ -102,7 +102,7 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
/* Read SATA controller mode from CMOS */
FchParams_env->Sata.SataClass = get_int_option("sata_mode", 0);
FchParams_env->Sata.SataClass = get_uint_option("sata_mode", 0);
switch ((SATA_CLASS)FchParams_env->Sata.SataClass) {
case SataLegacyIde:

6
src/mainboard/asus/p8z77-m_pro/early_init.c
View file

@ -69,15 +69,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
* 3 = Smart Auto : same than Auto, but if OS loads USB3 driver
* and reboots, it will keep the USB3.0 speed
*/
int usb3_mode = get_int_option("usb3_mode", 1);
unsigned int usb3_mode = get_uint_option("usb3_mode", 1);
usb3_mode &= 0x3; /* ensure it's 0/1/2/3 only */
/* Load USB3 pre-OS xHCI driver */
int usb3_drv = get_int_option("usb3_drv", 1);
unsigned int usb3_drv = get_uint_option("usb3_drv", 1);
usb3_drv &= 0x1; /* ensure it's 0/1 only */
/* Use USB3 xHCI streams */
int usb3_streams = get_int_option("usb3_streams", 1);
unsigned int usb3_streams = get_uint_option("usb3_streams", 1);
usb3_streams &= 0x1; /* ensure it's 0/1 only */
struct pei_data pd = {

2
src/mainboard/dell/optiplex_9010/sch5545_ec.c
View file

@ -656,7 +656,7 @@ void sch5545_ec_hwm_init(void *unused)
ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP);
unsigned int fan_speed_full = get_int_option("fan_full_speed", 0);
unsigned int fan_speed_full = get_uint_option("fan_full_speed", 0);
if (fan_speed_full) {
printk(BIOS_INFO, "Will set up fans to run at full speed\n");
ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP);

2
src/mainboard/getac/p470/early_init.c
View file

@ -35,7 +35,7 @@ void mainboard_lpc_decode(void)
{
int lpt_en = 0;
if (get_int_option("lpt", 0))
if (get_uint_option("lpt", 0))
lpt_en = LPT_LPC_EN; /* enable LPT */
// decode range

18
src/mainboard/ibase/mb899/superio_hwm.c
View file

@ -48,17 +48,17 @@ struct temperature temperatures[] = {
void hwm_setup(void)
{
int cpufan_control = 0, sysfan_control = 0;
int cpufan_speed = 0, sysfan_speed = 0;
int cpufan_temperature = 0, sysfan_temperature = 0;
unsigned int cpufan_control = 0, sysfan_control = 0;
unsigned int cpufan_speed = 0, sysfan_speed = 0;
unsigned int cpufan_temperature = 0, sysfan_temperature = 0;
cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625);
//cpufan_temperature = get_int_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC);
cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625);
//cpufan_temperature = get_uint_option("cpufan_temperature", FAN_TEMPERATURE_30DEGC);
sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625);
//sysfan_temperature = get_int_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC);
sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625);
//sysfan_temperature = get_uint_option("sysfan_temperature", FAN_TEMPERATURE_30DEGC);
// pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit
// pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit

2
src/mainboard/kontron/986lcd-m/early_init.c
View file

@ -15,7 +15,7 @@ void mainboard_lpc_decode(void)
{
int lpt_en = 0;
if (get_int_option("lpt", 0))
if (get_uint_option("lpt", 0))
lpt_en = LPT_LPC_EN; /* enable LPT */
pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);

16
src/mainboard/kontron/986lcd-m/mainboard.c
View file

@ -46,15 +46,15 @@ struct temperature temperatures[] = {
static void hwm_setup(void)
{
int cpufan_control = 0, sysfan_control = 0;
int cpufan_speed = 0, sysfan_speed = 0;
int cpufan_temperature = 0, sysfan_temperature = 0;
unsigned int cpufan_control = 0, sysfan_control = 0;
unsigned int cpufan_speed = 0, sysfan_speed = 0;
unsigned int cpufan_temperature = 0, sysfan_temperature = 0;
cpufan_control = get_int_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
cpufan_speed = get_int_option("cpufan_speed", FAN_SPEED_5625);
cpufan_control = get_uint_option("cpufan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
cpufan_speed = get_uint_option("cpufan_speed", FAN_SPEED_5625);
sysfan_control = get_int_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
sysfan_speed = get_int_option("sysfan_speed", FAN_SPEED_5625);
sysfan_control = get_uint_option("sysfan_cruise_control", FAN_CRUISE_CONTROL_DISABLED);
sysfan_speed = get_uint_option("sysfan_speed", FAN_SPEED_5625);
nuvoton_hwm_select_bank(hwm_base, 0);
pnp_write_hwm5_index(hwm_base, 0x59, 0x20); /* Diode Selection */
@ -139,7 +139,7 @@ static void mainboard_init(void *chip_info)
char cmos_option_name[] = "ethernetx";
snprintf(cmos_option_name, sizeof(cmos_option_name),
"ethernet%01d", i);
int ethernet_disable = get_int_option(cmos_option_name, 0);
unsigned int ethernet_disable = get_uint_option(cmos_option_name, 0);
if (!ethernet_disable)
continue;
printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i);

2
src/mainboard/kontron/bsl6/romstage.c
View file

@ -38,7 +38,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
memory_params->DqPinsInterleaved = true;
const uint8_t ht = get_int_option("hyper_threading", memory_params->HyperThreading);
const uint8_t ht = get_uint_option("hyper_threading", memory_params->HyperThreading);
memory_params->HyperThreading = ht;
variant_memory_init_params(mupd);

2
src/mainboard/kontron/bsl6/variants/boxer26/romstage.c
View file

@ -14,7 +14,7 @@ void variant_memory_init_params(FSPM_UPD *const mupd)
for (i = 0; i < 3; ++i) {
nvram_var[sizeof(nvram_var) - 2] = '1' + i;
u8 eth_enable = get_int_option(nvram_var, 1);
u8 eth_enable = get_uint_option(nvram_var, 1);
if (!eth_enable) {
printk(BIOS_INFO, "Disabling ethernet%u.\n", 1 + i);
mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8));

4
src/mainboard/kontron/ktqm77/mainboard.c
View file

@ -149,7 +149,7 @@ static void mainboard_enable(struct device *dev)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
unsigned int disable = get_int_option("ethernet1", 0);
unsigned int disable = get_uint_option("ethernet1", 0);
if (disable) {
struct device *nic = pcidev_on_root(0x1c, 2);
if (nic) {
@ -157,7 +157,7 @@ static void mainboard_enable(struct device *dev)
nic->enabled = 0;
}
}
disable = get_int_option("ethernet2", 0);
disable = get_uint_option("ethernet2", 0);
if (disable) {
struct device *nic = pcidev_on_root(0x1c, 3);
if (nic) {

2
src/mainboard/lenovo/t430s/variants/t430s/romstage.c
View file

@ -33,7 +33,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void mainboard_early_init(int s3resume)
{
u8 enable_peg = get_int_option("enable_dual_graphics", 0);
u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
bool power_en = pmh7_dgpu_power_state();

2
src/mainboard/lenovo/t440p/romstage.c
View file

@ -22,7 +22,7 @@ void mainboard_config_rcba(void)
void mb_late_romstage_setup(void)
{
u8 enable_peg = get_int_option("enable_dual_graphics", 0);
u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
bool power_en = pmh7_dgpu_power_state();

4
src/mainboard/lenovo/x60/smihandler.c
View file

@ -22,8 +22,8 @@ static void mainboard_smi_save_cmos(void)
tmp70 = inb(0x70);
tmp72 = inb(0x72);
set_int_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4));
set_int_option("volume", ec_read(H8_VOLUME_CONTROL));
set_uint_option("tft_brightness", pci_read_config8(PCI_DEV(0, 2, 1), 0xf4));
set_uint_option("volume", ec_read(H8_VOLUME_CONTROL));
outb(tmp70, 0x70);
outb(tmp72, 0x72);

2
src/mainboard/roda/rk886ex/early_init.c
View file

@ -17,7 +17,7 @@ void mainboard_lpc_decode(void)
{
int lpt_en = 0;
if (get_int_option("lpt", 0))
if (get_uint_option("lpt", 0))
lpt_en = LPT_LPC_EN; /* enable LPT */
pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);

4
src/mainboard/siemens/chili/romstage.c
View file

@ -24,9 +24,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
memupd->FspmConfig.EccSupport = 1;
memupd->FspmConfig.UserBd = BOARD_TYPE_MOBILE;
const uint8_t vtd = get_int_option("vtd", 1);
const uint8_t vtd = get_uint_option("vtd", 1);
memupd->FspmTestConfig.VtdDisable = !vtd;
const uint8_t ht = get_int_option("hyper_threading", memupd->FspmConfig.HyperThreading);
const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading);
memupd->FspmConfig.HyperThreading = ht;
variant_romstage_params(memupd);

2
src/mainboard/siemens/chili/variants/chili/romstage.c
View file

@ -7,7 +7,7 @@
void variant_romstage_params(FSPM_UPD *const mupd)
{
const uint8_t eth_enable = get_int_option("ethernet1", 1);
const uint8_t eth_enable = get_uint_option("ethernet1", 1);
if (!eth_enable) {
printk(BIOS_DEBUG, "Disabling ethernet1.\n");

2
src/mainboard/supermicro/x10slm-f/mainboard.c
View file

@ -30,7 +30,7 @@ static void hide_ast2400(void)
static void mainboard_enable(struct device *dev)
{
if (get_int_option("hide_ast2400", false))
if (get_uint_option("hide_ast2400", false))
hide_ast2400();
}

2
src/northbridge/intel/gm45/igd.c
View file

@ -116,7 +116,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo)
sysinfo->ggc = 0x0002;
else {
/* 4 for 32MB, default if not set in CMOS */
u8 gfxsize = get_int_option("gfx_uma_size", 4);
u8 gfxsize = get_uint_option("gfx_uma_size", 4);
/* Graphics Stolen Memory: 2MB GTT (0x0300) when VT-d disabled,
2MB GTT + 2MB shadow GTT (0x0b00) else. */

2
src/northbridge/intel/i945/early_init.c
View file

@ -149,7 +149,7 @@ static void i945_setup_bars(void)
pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1);
/* vram size from CMOS option */
gfxsize = get_int_option("gfx_uma_size", 2); /* 2 for 8MB */
gfxsize = get_uint_option("gfx_uma_size", 2); /* 2 for 8MB */
/* make sure no invalid setting is used */
if (gfxsize > 6)
gfxsize = 2;

2
src/northbridge/intel/i945/gma.c
View file

@ -710,7 +710,7 @@ static void gma_func1_init(struct device *dev)
if (!CONFIG(NO_GFX_INIT))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config8(dev, 0xf4, get_int_option("tft_brightness", 0xff));
pci_write_config8(dev, 0xf4, get_uint_option("tft_brightness", 0xff));
}
static void gma_generate_ssdt(const struct device *device)

2
src/northbridge/intel/ironlake/raminit.c
View file

@ -3102,7 +3102,7 @@ void chipset_init(const int s3resume)
mchbar_write16(0x1170, 0xb880);
mchbar_clrsetbits8(0x1210, ~0, 0x84);
gfxsize = get_int_option("gfx_uma_size", 0); /* 0 for 32MB */
gfxsize = get_uint_option("gfx_uma_size", 0); /* 0 for 32MB */
ggc = 0xb00 | ((gfxsize + 5) << 4);

2
src/northbridge/intel/pineview/early_init.c
View file

@ -25,7 +25,7 @@ static void early_graphics_setup(void)
pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN);
/* Fetch VRAM size from CMOS option */
reg8 = get_int_option("gfx_uma_size", 0); /* 0 for 8MB */
reg8 = get_uint_option("gfx_uma_size", 0); /* 0 for 8MB */
/* Ensure the setting is valid */
if (reg8 > 6)

2
src/northbridge/intel/sandybridge/early_init.c
View file

@ -87,7 +87,7 @@ static void sandybridge_setup_graphics(void)
printk(BIOS_DEBUG, "Initializing Graphics...\n");
/* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */
gfxsize = get_int_option("gfx_uma_size", 0);
gfxsize = get_uint_option("gfx_uma_size", 0);
reg16 = pci_read_config16(HOST_BRIDGE, GGC);
reg16 &= ~0x00f8;

2
src/northbridge/intel/x4x/early_init.c
View file

@ -39,7 +39,7 @@ void x4x_early_init(void)
pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
/* Set preallocated IGD size from CMOS, or default to 64 MiB */
u8 gfxsize = get_int_option("gfx_uma_size", 6);
u8 gfxsize = get_uint_option("gfx_uma_size", 6);
if (gfxsize > 12)
gfxsize = 6;
/* Need at least 4M for cbmem_top alignment */

2
src/soc/intel/broadwell/pch/lpc.c
View file

@ -132,7 +132,7 @@ static void pch_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use Kconfig setting.
*/
const int pwr_on = get_int_option("power_on_after_fail",
const unsigned int pwr_on = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3);

2
src/soc/intel/broadwell/pch/smihandler.c
View file

@ -131,7 +131,7 @@ static int power_on_after_fail(void)
u8 tmp70, tmp72;
tmp70 = inb(0x70);
tmp72 = inb(0x72);
const int s5pwr = get_int_option("power_on_after_fail",
const unsigned int s5pwr = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
outb(tmp70, 0x70);
outb(tmp72, 0x72);

2
src/soc/intel/common/block/pmc/pmclib.c
View file

@ -583,7 +583,7 @@ void pmc_set_power_failure_state(const bool target_on)
{
bool on;
const int state = get_int_option("power_on_after_fail",
const unsigned int state = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
switch (state) {

4
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -169,7 +169,7 @@ static void pch_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use Kconfig setting.
*/
const int pwr_on = get_int_option("power_on_after_fail",
const unsigned int pwr_on = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3);
@ -211,7 +211,7 @@ static void pch_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

6
src/southbridge/intel/bd82x6x/me.c
View file

@ -184,8 +184,8 @@ static void intel_me_init(struct device *dev)
/* Do initial setup and determine the BIOS path */
printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
u8 me_state = get_int_option("me_state", 0);
u8 me_state_prev = get_int_option("me_state_prev", 0);
u8 me_state = get_uint_option("me_state", 0);
u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@ -268,7 +268,7 @@ static void intel_me_init(struct device *dev)
set the 'changed' bit here. */
if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) {
u8 new_state = me_state | CMOS_ME_STATE_CHANGED;
set_int_option("me_state_prev", new_state);
set_uint_option("me_state_prev", new_state);
}
if (need_reset) {

6
src/southbridge/intel/bd82x6x/me_8.x.c
View file

@ -182,8 +182,8 @@ static void intel_me_init(struct device *dev)
/* Do initial setup and determine the BIOS path */
printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
u8 me_state = get_int_option("me_state", 0);
u8 me_state_prev = get_int_option("me_state_prev", 0);
u8 me_state = get_uint_option("me_state", 0);
u8 me_state_prev = get_uint_option("me_state_prev", 0);
printk(BIOS_DEBUG, "ME: me_state=%u, me_state_prev=%u\n", me_state, me_state_prev);
@ -267,7 +267,7 @@ static void intel_me_init(struct device *dev)
set the 'changed' bit here. */
if (me_state != CMOS_ME_STATE(me_state_prev) || need_reset) {
u8 new_state = me_state | CMOS_ME_STATE_CHANGED;
set_int_option("me_state_prev", new_state);
set_uint_option("me_state_prev", new_state);
}
if (need_reset) {

8
src/southbridge/intel/bd82x6x/sata.c
View file

@ -35,7 +35,7 @@ static void sata_read_resources(struct device *dev)
/* Assign fixed resources for IDE legacy mode */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
if (sata_mode != 2)
return;
@ -71,7 +71,7 @@ static void sata_read_resources(struct device *dev)
static void sata_set_resources(struct device *dev)
{
/* work around bug in pci_dev_set_resources(), it bails out on FIXED */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
if (sata_mode == 2) {
unsigned int i;
for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_3; i += 4) {
@ -99,7 +99,7 @@ static void sata_init(struct device *dev)
}
/* Default to AHCI */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/* SATA configuration */
@ -230,7 +230,7 @@ static void sata_enable(struct device *dev)
if (!config)
return;
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* Set SATA controller mode early so the resource allocator can

2
src/southbridge/intel/common/smihandler.c
View file

@ -99,7 +99,7 @@ static int power_on_after_fail(void)
u8 tmp70, tmp72;
tmp70 = inb(0x70);
tmp72 = inb(0x72);
const int s5pwr = get_int_option("power_on_after_fail",
const unsigned int s5pwr = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
outb(tmp70, 0x70);
outb(tmp72, 0x72);

4
src/southbridge/intel/i82801dx/lpc.c
View file

@ -94,7 +94,7 @@ static void i82801dx_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON);
const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
@ -129,7 +129,7 @@ static void i82801dx_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/i82801gx/lpc.c
View file

@ -157,7 +157,7 @@ static void i82801gx_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON);
const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
@ -193,7 +193,7 @@ static void i82801gx_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/i82801ix/lpc.c
View file

@ -162,7 +162,7 @@ static void i82801ix_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON);
const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
reg8 &= 0xfe;
@ -198,7 +198,7 @@ static void i82801ix_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/i82801ix/sata.c
View file

@ -152,7 +152,7 @@ static void sata_init(struct device *const dev)
}
/* Default to AHCI */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* TODO: In contrast to ICH7 and PCH code we don't set
@ -227,7 +227,7 @@ static void sata_enable(struct device *dev)
if (!config)
return;
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* Set SATA controller mode early so the resource allocator can

4
src/southbridge/intel/i82801jx/lpc.c
View file

@ -164,7 +164,7 @@ static void i82801jx_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON);
const unsigned int pwr_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_ON);
reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3);
reg8 &= 0xfe;
@ -200,7 +200,7 @@ static void i82801jx_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/i82801jx/sata.c
View file

@ -139,7 +139,7 @@ static void sata_init(struct device *const dev)
}
/* Default to AHCI */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* TODO: In contrast to ICH7 and PCH code we don't set
@ -205,7 +205,7 @@ static void sata_enable(struct device *dev)
return;
/* Default to AHCI */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* Set SATA controller mode early so the resource allocator can

4
src/southbridge/intel/ibexpeak/lpc.c
View file

@ -162,7 +162,7 @@ static void pch_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use Kconfig setting.
*/
const int pwr_on = get_int_option("power_on_after_fail",
const unsigned int pwr_on = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3);
@ -204,7 +204,7 @@ static void pch_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/ibexpeak/sata.c
View file

@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
}
/* Default to AHCI */
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/* SATA configuration */
@ -174,7 +174,7 @@ static void sata_enable(struct device *dev)
if (!config)
return;
u8 sata_mode = get_int_option("sata_mode", 0);
u8 sata_mode = get_uint_option("sata_mode", 0);
/*
* Set SATA controller mode early so the resource allocator can

4
src/southbridge/intel/lynxpoint/lpc.c
View file

@ -193,7 +193,7 @@ static void pch_power_options(struct device *dev)
*
* If the option is not existent (Laptops), use Kconfig setting.
*/
const int pwr_on = get_int_option("power_on_after_fail",
const unsigned int pwr_on = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
reg16 = pci_read_config16(dev, GEN_PMCON_3);
@ -235,7 +235,7 @@ static void pch_power_options(struct device *dev)
outb(reg8, 0x61);
reg8 = inb(0x70);
const int nmi_option = get_int_option("nmi", NMI_OFF);
const unsigned int nmi_option = get_uint_option("nmi", NMI_OFF);
if (nmi_option) {
printk(BIOS_INFO, "NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

2
src/southbridge/intel/lynxpoint/smihandler.c
View file

@ -82,7 +82,7 @@ static int power_on_after_fail(void)
u8 tmp70, tmp72;
tmp70 = inb(0x70);
tmp72 = inb(0x72);
const int s5pwr = get_int_option("power_on_after_fail",
const unsigned int s5pwr = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
outb(tmp70, 0x70);
outb(tmp72, 0x72);

2
src/superio/ite/it8720f/superio.c
View file

@ -17,7 +17,7 @@
static void power_control_init(struct device *dev)
{
int power_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_OFF);
unsigned int power_on = get_uint_option("power_on_after_fail", MAINBOARD_POWER_OFF);
u8 value;
pnp_enter_conf_mode(dev);

2
src/superio/nuvoton/nct5572d/superio.c
View file

@ -47,7 +47,7 @@ static void nct5572d_init(struct device *dev)
break;
case NCT5572D_ACPI:
/* Set power state after power fail */
power_status = get_int_option("power_on_after_fail",
power_status = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);

2
src/superio/nuvoton/npcd378/superio.c
View file

@ -68,7 +68,7 @@ static void npcd378_init(struct device *dev)
npcd378_hwm_write_start(res->base);
unsigned int fan_lvl = get_int_option("psu_fan_lvl", 3);
unsigned int fan_lvl = get_uint_option("psu_fan_lvl", 3);
if (fan_lvl > 7)
fan_lvl = 3;

2
src/superio/winbond/w83627ehg/superio.c
View file

@ -23,7 +23,7 @@ static void enable_hwm_smbus(struct device *dev)
static void init_acpi(struct device *dev)
{
u8 value;
int power_on = get_int_option("power_on_after_fail", 1);
unsigned int power_on = get_uint_option("power_on_after_fail", 1);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);

2
src/superio/winbond/w83627hf/superio.c
View file

@ -23,7 +23,7 @@ static void enable_hwm_smbus(struct device *dev)
static void init_acpi(struct device *dev)
{
u8 value;
int power_on = get_int_option("power_on_after_fail", 1);
unsigned int power_on = get_uint_option("power_on_after_fail", 1);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);

2
src/superio/winbond/w83667hg-a/superio.c
View file

@ -47,7 +47,7 @@ static void w83667hg_a_init(struct device *dev)
break;
case W83667HG_A_ACPI:
/* Set power state after power fail */
power_status = get_int_option("power_on_after_fail",
power_status = get_uint_option("power_on_after_fail",
CONFIG_MAINBOARD_POWER_FAILURE_STATE);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);