soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb
BUG=chrome-os-partner:56034 Change-Id: Id88d262b32dea468536575117fc34d52076a3096 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -400,6 +400,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
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/* Disable FSP from locking access to the RTC NVRAM */
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silconfig->RtcLock = 0;
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/* Enable Audio clk gate and power gate */
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silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
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silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
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/* Bios config lockdown Audio clk and power gate */
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silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
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}
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struct chip_operations soc_intel_apollolake_ops = {
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@ -107,6 +107,13 @@ struct soc_intel_apollolake_config {
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/* Enable DPTF support */
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int dptf_enable;
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/* Configure Audio clk gate and power gate
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* IOSF-SB port ID 92 offset 0x530 [5] and [3]
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*/
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uint8_t hdaudio_clk_gate_enable;
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uint8_t hdaudio_pwr_gate_enable;
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uint8_t hdaudio_bios_config_lockdown;
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/* SLP S3 minimum assertion width. */
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int slp_s3_assertion_width_usecs;
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};
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